Datasheet

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7.1.2 Definition of Terms............................................................................................... 332
7.1.3 F021 Flash Tools ................................................................................................ 333
7.2 Default Flash Configuration ............................................................................................. 333
7.3 EEPROM Emulation Support............................................................................................ 333
7.4 SECDED ................................................................................................................... 334
7.4.1 SECDED Initialization ........................................................................................... 334
7.4.2 ECC Encoding.................................................................................................... 334
7.4.3 Syndrome Table: Decode to Bit in Error...................................................................... 336
7.4.4 Syndrome Table: An Alternate Method ....................................................................... 337
7.5 Memory Map .............................................................................................................. 338
7.5.1 Location of Flash ECC Bits..................................................................................... 338
7.5.2 OTP Memory ..................................................................................................... 339
7.6 Deliberate ECC Errors for FMC ECC Checking ...................................................................... 342
7.7 Power On, Power Off Considerations.................................................................................. 343
7.7.1 Error Checking at Power On ................................................................................... 343
7.7.2 Flash Integrity at Power Off .................................................................................... 343
7.8 Emulation and SIL3 Diagnostic Modes ................................................................................ 343
7.8.1 System Emulation ............................................................................................... 343
7.8.2 Diagnostic Mode ................................................................................................. 343
7.8.3 Diagnostic Mode Summary..................................................................................... 345
7.8.4 SECDED Software Diagnostic ................................................................................. 346
7.8.5 Read Margin...................................................................................................... 346
7.9 Parameter Overlay Module (POM) ..................................................................................... 346
7.9.1 Example Procedure to Configure the POM .................................................................. 346
7.10 Summary of L2FMC Errors.............................................................................................. 347
7.11 Flash Control Registers .................................................................................................. 348
7.11.1 Flash Read Control Register (FRDCNTL)................................................................... 349
7.11.2 EEPROM Error Correction Control Register (EE_FEDACCTRL1)....................................... 350
7.11.3 Flash PortA Error and Status Register (FEDAC_PASTATUS) ........................................... 351
7.11.4 Flash PortB Error and Status Register (FEDAC_PBSTATUS) ........................................... 352
7.11.5 Flash Global Error and Status Register (FEDAC_GBLSTATUS) ........................................ 353
7.11.6 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)......................... 354
7.11.7 Primary Address Tag Register (FPRIM_ADD_TAG)....................................................... 355
7.11.8 Duplicate Address Tag Register (FDUP_ADD_TAG)...................................................... 355
7.11.9 Flash Bank Protection Register (FBPROT) ................................................................. 356
7.11.10 Flash Bank Sector Enable Register (FBSE)............................................................... 356
7.11.11 Flash Bank Busy Register (FBBUSY) ...................................................................... 357
7.11.12 Flash Bank Access Control Register (FBAC) ............................................................. 357
7.11.13 Flash Bank Power Mode Register (FBPWRMODE) ..................................................... 358
7.11.14 Flash Bank/Pump Ready Register (FBPRDY) ............................................................ 359
7.11.15 Flash Pump Access Control Register 1 (FPAC1)......................................................... 360
7.11.16 Flash Module Access Control Register (FMAC) .......................................................... 361
7.11.17 Flash Module Status Register (FMSTAT).................................................................. 362
7.11.18 EEPROM Emulation Data MSW Register (FEMU_DMSW) ............................................. 364
7.11.19 EEPROM Emulation Data LSW Register (FEMU_DLSW)............................................... 364
7.11.20 EEPROM Emulation ECC Register (FEMU_ECC) ....................................................... 365
7.11.21 Flash Lock Register (FLOCK) ............................................................................... 365
7.11.22 Diagnostic Control Register (FDIAGCTRL)................................................................ 366
7.11.23 Raw Address Register (FRAW_ADDR) ................................................................... 367
7.11.24 Parity Override Register (FPAR_OVR)..................................................................... 368
7.11.25 Reset Configuration Valid Register (RCR_VALID) ....................................................... 369
7.11.26 Crossbar Access Time Threshold Register (ACC_THRESHOLD) ..................................... 369
7.11.27 Flash Error Detection and Correction Sector Disable Register 2 (FEDACSDIS2) ................... 370
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SPNU563–May 2014 Contents
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