Datasheet
Contents
Preface..................................................................................................................................... 102
1 Introduction ..................................................................................................................... 103
1.1 Designed for Safety Applications ....................................................................................... 104
1.2 Family Description ........................................................................................................ 105
1.3 Endianism Considerations............................................................................................... 108
1.3.1 TMS570: Big Endian (BE32) ................................................................................... 108
2 Architecture ..................................................................................................................... 109
2.1 Introduction ................................................................................................................ 110
2.1.1 Architecture Block Diagram .................................................................................... 110
2.1.2 Definitions of Terms ............................................................................................. 112
2.1.3 Bus Master / Slave Access Privileges ........................................................................ 115
2.1.4 CPU Interconnect Subsystem SDC MMR Port .............................................................. 115
2.1.5 Interconnect Subsystem Runtime Status ..................................................................... 116
2.1.6 Master ID to PCRx............................................................................................... 116
2.2 Memory Organization .................................................................................................... 117
2.2.1 Memory Map Overview ......................................................................................... 117
2.2.2 Memory Map Table .............................................................................................. 119
2.2.3 Flash on Microcontrollers ....................................................................................... 126
2.2.4 On-Chip SRAM................................................................................................... 131
2.3 Exceptions ................................................................................................................. 136
2.3.1 Resets............................................................................................................. 136
2.3.2 Aborts ............................................................................................................. 136
2.3.3 System Software Interrupts..................................................................................... 138
2.4 Clocks ...................................................................................................................... 139
2.4.1 Clock Sources.................................................................................................... 139
2.4.2 Clock Domains ................................................................................................... 140
2.4.3 Low Power Modes ............................................................................................... 142
2.4.4 Clock Test Mode ................................................................................................. 143
2.4.5 Embedded Trace Macrocell (ETM-R5)........................................................................ 145
2.4.6 Safety Considerations for Clocks .............................................................................. 145
2.5 System and Peripheral Control Registers ............................................................................. 148
2.5.1 Primary System Control Registers (SYS) .................................................................... 148
2.5.2 Secondary System Control Registers (SYS2) ............................................................... 200
2.5.3 Peripheral Central Resource (PCR) Control Registers .................................................... 212
3 SCR Control Module (SCM) ................................................................................................ 246
3.1 Overview ................................................................................................................... 247
3.1.1 Features........................................................................................................... 247
3.1.2 System Block Diagram .......................................................................................... 248
3.2 Module Operation......................................................................................................... 249
3.2.1 Block Diagram.................................................................................................... 249
3.2.2 Timeout Threshold Compare Block ........................................................................... 249
3.2.3 SCM Control Block .............................................................................................. 250
3.3 How to Use SCM ......................................................................................................... 251
3.3.1 How to Check the Parity Compare Logic ..................................................................... 251
3.3.2 How to Initiate Self-test Sequence ............................................................................ 252
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Contents SPNU563–May 2014
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