Datasheet

Control Registers

www.ti.com

36.3 Control Registers

This section describes the DMM registers. The registers support 8, 16, and 32-bit writes. The offset is

relative to the associated peripheral select. Table 36-6 provides a summary of the registers and their bits.

The base address of the DMM module registers is FFFF F700h.

Table 36-6. DMM Registers

Offset Acronym Register Description Section

0 DMMGLBCTRL DMM Global Control Register Section 36.3.1

4h DMMINTSET DMM Interrupt Set Register Section 36.3.2

8h DMMINTCLR DMM Interrupt Clear Register Section 36.3.3

0Ch DMMINTLVL DMM Interrupt Level Register Section 36.3.4

10h DMMINTFLG DMM Interrupt Flag Register Section 36.3.5

14h DMMOFF1 DMM Interrupt Offset 1 Register Section 36.3.6

18h DMMOFF2 DMM Interrupt Offset 2 Register Section 36.3.7

1Ch DMMDDMDEST DMM Direct Data Mode Destination Register Section 36.3.8

20h DMMDDMBL DMM Direct Data Mode Blocksize Register Section 36.3.9

24h DMMDDMPT DMM Direct Data Mode Pointer Register Section 36.3.10

28h DMMINTPT DMM Direct Data Mode Interrupt Pointer Register Section 36.3.11

2Ch, 3Ch, 4Ch, 5Ch DMMDESTxREG1 DMM Destination x Region 1 Section 36.3.12

30h, 40h, 50h, 60h DMMDESTxBL1 DMM Destination x Blocksize 1 Section 36.3.13

34h, 44h, 54h, 64h DMMDESTxREG2 DMM Destination x Region 2 Section 36.3.14

38h, 48h, 58h, 68h DMMDESTxBL2 DMM Destination x Blocksize 2 Section 36.3.15

6Ch DMMPC0 DMM Pin Control 0 Section 36.3.16

70h DMMPC1 DMM Pin Control 1 Section 36.3.17

74h DMMPC2 DMM Pin Control 2 Section 36.3.18

78h DMMPC3 DMM Pin Control 3 Section 36.3.19

7Ch DMMPC4 DMM Pin Control 4 Section 36.3.20

80h DMMPC5 DMM Pin Control 5 Section 36.3.21

84h DMMPC6 DMM Pin Control 6 Section 36.3.22

88h DMMPC7 DMM Pin Control 7 Section 36.3.23

8Ch DMMPC8 DMM Pin Control 8 Section 36.3.24

2048

Data Modification Module (DMM) SPNU563–May 2014

Submit Documentation Feedback