Datasheet

8, 16, or 32 bit
HWDATA(xx–0)
2+2+2+18+2 x8 bit
SIZE
DEST(1–0) STAT(1–0) SIZE(1–0) ADDR(17–0) DATA(xx–0)
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The DEST bits (Table 36-1) will be used to determine which destination register applies to the transmitted
data and the received address determines if the packet falls into a valid region of the destination area. If
the address is valid, the base address, programmed in one of the destination registers (Section 36.3.12 ;
Section 36.3.14) of this particular region will be applied to create the complete 32-bit address for the
destination. The DMM module only takes action on a "11" setting of the STAT bits (Table 36-2). This
signals that an overflow in the transmitting hardware module has occurred. If this is the case the
SRC_OVF flag (Section 36.3.5) will be set and the received data will be written to the address specified in
the packet. The size information of the data transmitted in the packet is denoted in the SIZE bits
(Table 36-3) of the packet. Depending on the SIZE information, the module expects to receive only this
amount of data.
Figure 36-2. Trace Mode Packet Format
Table 36-1 through Table 36-3 illustrate the encoding of packet format in trace mode.
Table 36-1. Encoding of Destination Bits in Trace Mode Packet Format
DEST[1:0] Destination
00 Dest 0
01 Dest 1
10 Dest 2
11 Dest 3
Table 36-2. Encoding of Status Bits in Trace Mode Packet Format
STAT[1:0] Status
00 don't care
01 don't care
10 don't care
11 overflow
Table 36-3. Encoding of Write Size in Packet Format
SIZE[1:0] Write Size
00 8 bit
01 16 bit
10 32 bit
11 64 bit
36.2.1.3 Direct Data Mode Packet
Figure 36-3 illustrates the direct data mode packet format.
Figure 36-3. Direct Data Mode Packet Format
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Data Modification Module (DMM) SPNU563–May 2014
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