Datasheet

SIZE ADDRESS ATA
DATA
DATA
ADDRESS
BASEADDR
SIZE
To Main SCR
Control
SIZESTATDEST ADDR ATA DATA
31
0
63
0
87 0
Buffer2
Buffer1
Memory protection
(destination registers)
Deserializer
…
Overview www.ti.com
36.1 Overview
36.1.1 Features
The DMM module has the following features:
• Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention
• Writes to memory locations specified in the received packet (leverages packets defined by trace mode
of the RAM trace port (RTP) module
• Writes received data to consecutive addresses, which are specified by the DMM module (leverages
packets defined by direct data mode of RTP module)
• Configurable port width (1, 2, 4, 8, 16 pins)
• Up to 100 Mbit/s pin data rate
• Unused pins configurable as GIO pins
36.1.2 Block Diagram
Figure 36-1 shows the block diagram for the DMM.
Figure 36-1. DMM Block Diagram
2042
Data Modification Module (DMM) SPNU563–May 2014
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