Datasheet

ePWM Registers

www.ti.com

35.4.6.4 Event-Trigger Force Register (ETFRC)

Figure 35-88. Event-Trigger Force Register (ETFRC) [offset = 38h]

15 8

Reserved

R-0

7 4 3 2 1 0

Reserved SOCB SOCA Reserved INT

R-0 R/W-0 R/W-0 R-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35-48. Event-Trigger Force Register (ETFRC) Field Descriptions

Bits Name Value Description

15-4 Reserved 0 Reserved

3 SOCB SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL

0 Has no effect. Always reads back a 0.

1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit. This bit is used for test purposes.

2 SOCA SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL

0 Writing 0 to this bit will be ignored. Always reads back a 0.

1 Generates a pulse on EPWMxSOCA and set the SOCAFLG bit. This bit is used for test purposes.

1 Reserved 0 Reserved

0 INT INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register.

The INT flag bit will be set regardless.

0 Writing 0 to this bit will be ignored. Always reads back a 0.

1 Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes.

2030

Enhanced Pulse Width Modulator (ePWM) Module SPNU563–May 2014

Submit Documentation Feedback