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eCAP Registers
33.5 eCAP Registers
Table 33-1 shows the eCAP module control and status registers. The base address for the control
registers is FCF7 9300h for eCAP1, FCF7 9400h for eCAP2, FCF7 9500h for eCAP3, FCF7 9600h for
eCAP4, FCF7 9700h for eCAP5, and FCF7 9800h for eCAP6.
Table 33-1. ECAP Control and Status Registers
Address Offset Acronym Description Section
00h TSCTR Time-Stamp Counter Register Section 33.5.1
04h CTRPHS Counter Phase Offset Value Register Section 33.5.2
08h CAP1 Capture 1 Register Section 33.5.3
0Ch CAP2 Capture 2 Register Section 33.5.4
10h CAP3 Capture 3 Register Section 33.5.5
14h CAP4 Capture 4 Register Section 33.5.6
28h ECCTL2 Capture Control Register 2 Section 33.5.7
2Ah ECCTL1 Capture Control Register 1 Section 33.5.8
2Ch ECFLG Capture Interrupt Flag Register Section 33.5.9
2Eh ECEINT Capture Interrupt Enable Register Section 33.5.10
30h ECFRC Capture Interrupt Forcing Register Section 33.5.11
32h ECCLR Capture Interrupt Clear Register Section 33.5.12
33.5.1 Time-Stamp Counter Register (TSCTR)
Figure 33-14. Time-Stamp Counter Register (TSCTR) [offset = 00h]
31 0
TSCTR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33-2. Time-Stamp Counter Register (TSCTR) Field Descriptions
Bits Field Description
31-0 TSCTR Active 32-bit counter register that is used as the capture time-base
33.5.2 Counter Phase Control Register (CTRPHS)
Figure 33-15. Counter Phase Control Register (CTRPHS) [offset = 04h]
31 0
CTRPHS
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33-3. Counter Phase Control Register (CTRPHS) Field Descriptions
Bits Field Description
31-0 CTRPHS Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCTR and is
loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control
synchronization with respect to other eCAP and EPWM time-bases.
1879
SPNU563–May 2014 Enhanced Capture (eCAP) Module
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