Datasheet

EMAC Module Registers www.ti.com
32.5.33 MAC Configuration Register (MACCONFIG)
The MAC configuration register (MACCONFIG) is shown in Figure 32-71 and described in Table 32-72.
Figure 32-71. MAC Configuration Register (MACCONFIG) (offset = 170h)
31 24 23 16
TXCELLDEPTH RXCELLDEPTH
R-3h R-3h
15 8 7 0
ADDRESSTYPE MACCFIG
R-2h R-2h
LEGEND: R = Read only; -n = value after reset
Table 32-72. MAC Configuration Register (MACCONFIG) Field Descriptions
Bit Field Value Description
31-24 TXCELLDEPTH 3h Transmit cell depth. These bits indicate the number of cells in the transmit FIFO.
23-16 RXCELLDEPTH 3h Receive cell depth. These bits indicate the number of cells in the receive FIFO.
15-8 ADDRESSTYPE 2h Address type
7-0 MACCFIG 2h MAC configuration value
32.5.34 Soft Reset Register (SOFTRESET)
The soft reset register (SOFTRESET) is shown in Figure 32-72 and described in Table 32-73.
Figure 32-72. Soft Reset Register (SOFTRESET) (offset = 174h)
31 16
Reserved
R-0
15 1 0
Reserved SOFTRESET
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32-73. Soft Reset Register (SOFTRESET) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 SOFTRESET Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. Software reset occurs
when the receive and transmit DMA controllers are in an idle state to avoid locking up the
Configuration bus. After writing a 1 to this bit, it may be polled to determine if the reset has
occurred. If a 1 is read, the reset has not yet occurred. If a 0 is read, then a reset has occurred.
0 A software reset has not occurred.
1 A software reset has occurred.
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EMAC/MDIO Module SPNU563–May 2014
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