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EMAC Module Registers

32.5 EMAC Module Registers

Table 32-39 lists the memory-mapped registers for the EMAC. The base address for these registers is

FCF7 8000h.

Table 32-39. Ethernet Media Access Controller (EMAC) Registers

Offset Acronym Register Description Section

0h TXREVID Transmit Revision ID Register Section 32.5.1

4h TXCONTROL Transmit Control Register Section 32.5.2

8h TXTEARDOWN Transmit Teardown Register Section 32.5.3

10h RXREVID Receive Revision ID Register Section 32.5.4

14h RXCONTROL Receive Control Register Section 32.5.5

18h RXTEARDOWN Receive Teardown Register Section 32.5.6

80h TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register Section 32.5.7

84h TXINTSTATMASKED Transmit Interrupt Status (Masked) Register Section 32.5.8

88h TXINTMASKSET Transmit Interrupt Mask Set Register Section 32.5.9

8Ch TXINTMASKCLEAR Transmit Interrupt Clear Register Section 32.5.10

90h MACINVECTOR MAC Input Vector Register Section 32.5.11

94h MACEOIVECTOR MAC End Of Interrupt Vector Register Section 32.5.12

A0h RXINTSTATRAW Receive Interrupt Status (Unmasked) Register Section 32.5.13

A4h RXINTSTATMASKED Receive Interrupt Status (Masked) Register Section 32.5.14

A8h RXINTMASKSET Receive Interrupt Mask Set Register Section 32.5.15

ACh RXINTMASKCLEAR Receive Interrupt Mask Clear Register Section 32.5.16

B0h MACINTSTATRAW MAC Interrupt Status (Unmasked) Register Section 32.5.17

B4h MACINTSTATMASKED MAC Interrupt Status (Masked) Register Section 32.5.18

B8h MACINTMASKSET MAC Interrupt Mask Set Register Section 32.5.19

BCh MACINTMASKCLEAR MAC Interrupt Mask Clear Register Section 32.5.20

100h RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Section 32.5.21

104h RXUNICASTSET Receive Unicast Enable Set Register Section 32.5.22

108h RXUNICASTCLEAR Receive Unicast Clear Register Section 32.5.23

10Ch RXMAXLEN Receive Maximum Length Register Section 32.5.24

110h RXBUFFEROFFSET Receive Buffer Offset Register Section 32.5.25

114h RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register Section 32.5.26

120h RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register Section 32.5.27

124h RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register Section 32.5.27

128h RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register Section 32.5.27

12Ch RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register Section 32.5.27

130h RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register Section 32.5.27

134h RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register Section 32.5.27

138h RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register Section 32.5.27

13Ch RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register Section 32.5.27

140h RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register Section 32.5.28

144h RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register Section 32.5.28

148h RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register Section 32.5.28

14Ch RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register Section 32.5.28

150h RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register Section 32.5.28

154h RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register Section 32.5.28

158h RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register Section 32.5.28

15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 32.5.28

160h MACCONTROL MAC Control Register Section 32.5.29

1813

SPNU563–May 2014 EMAC/MDIO Module

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