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I2C Control Registers

31.6.1 I2C Own Address Manager (I2COAR)

The 16-bit memory-mapped I2C own address register is used to specify its own address. Figure 31-13

and Table 31-4 describe this register.

Figure 31-13. I2C Own Address Manager Register (I2COAR) [offset = 00]

15 10 9 0

Reserved OA

R-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31-4. I2C Own Address Manager Register (I2COAR) Field Descriptions

Bit Field Value Description

15-10 Reserved 0 Read returns 0. Writes have no effect.

9-0 OA 0-3FFh Own address

These bits reflect the bus address of the I2C module. When the expand address (XA) bit

I2CMDR.8 is set to 1, the I2C is in expand address mode (10-bit addressing mode). In either 7

or 10-bit address mode, all 10-bits are both readable and writable. Bits 7, 8, and 9 should only

be used in 10-bit address mode. Table 31-5 provides the correct modes for these bits. Note that

the user can program the I2C own address to any value as long as it does not conflict with

other components in the system.

Table 31-5. Correct Mode for OA Bits

Bits Used Mode Value of XA

OA.6:0 7 Bit Addressing 0

OA.9:0 10 Bit Addressing 1

1719

SPNU563–May 2014 Inter-Integrated Circuit (I2C) Module

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