Datasheet
1 1
8 8 1 8 1
1
S
Data
ACK P
Data Data
ACKACK
I2C Module Operation
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31.2.5.4 Free Data Format
In this format (Figure 31-10), the first byte after a START condition is a data byte. The ACK bit is inserted
after each byte, followed by another 8 bits of data. No address or data direction bit is sent. Therefore, the
transmitter and receiver must both support the free data format. The direction of data transmission
(transmit or receive) remains constant throughout the transfer.
To select the free data format, write a 1 to the free data format (FDF) bit of the I2CMDR. The free data
format is not supported in the digital loop back mode.
Figure 31-10. I2C Module in Free Data Format
31.2.6 NACK Bit Generation
When the I2C module is a receiver (master or slave), it can acknowledge or ignore bits sent by the
transmitter. To ignore any new bits, the I2C module must send a no-acknowledge (NACK) bit during the
acknowledge cycle on the bus. Table 31-1 summarizes the various ways a NACK can be generated.
Table 31-1. Ways to Generate a NACK Bit
I2C Module Condition Basic NACK Bit Generation Options Additional Option
Slave receiver mode Disable data transfers (STT = 0) Set the NACKMOD bit before the rising
Allow an overrun condition (RSFULL = 1) edge of the last data bit you intend to
Reset the module (IRS = 0) receive.
Master receiver mode and repeat Generate a STOP condition (STP = 1) Set the NACKMOD bit before the rising
mode (RM = 1) Reset the module (IRS = 0) edge of the last data bit you intend to
receive.
Master receiver mode with non-repeat If STP = 1, allow the internal data counter to Set the NACKMOD bit before the rising
mode (RM = 0) count down to 0 and thus force a STOP edge of the last data bit you intend to
condition. receive.
If STP = 0, make STP = 1 to generate a
STOP condition.
Reset the module (IRS = 0)
In some applications, the slave cannot generate the ACK signal. If the IGNACK bit is set in the I2CEMDR
register, the resulting NACK will be ignored and the I2C block will continue the data transfer.
1710
Inter-Integrated Circuit (I2C) Module SPNU563–May 2014
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