Datasheet

186
TMS570LC4357
SPNS195C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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Peripheral Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
(1) This parameter will be characterized, but not production-tested.
(2) This value is based on design simulation.
Table 7-28. FlexRay Jitter Timing
(1)
PARAMETER MIN MAX UNIT
t
Tx1bit
Clock jitter and signal symmetry 98 102 ns
t
Tx10bit
FlexRay BSS (byte start sequence) to BSS 999 1001 ns
t
Tx10bitAvg
Average over 10000 samples 999.5 1000.5 ns
t
RxAsymDelay
(2)
Delay difference between rise and fall from Rx pin to sample
point in FlexRay core
– 2.5 ns
t
jit(SCLK)
Jitter for the 80-MHz Sample Clock generated by the PLL – 0.5 ns
7.7.3 FlexRay Transfer Unit
The FlexRay Transfer Unit is able to transfer data between the input buffer (IBF) and output buffer (OBF)
of the communication controller and the system memory without CPU interaction.
Because the FlexRay module is accessed through the FTU, the FTU must be powered up by the setting
bit 23 in the Peripheral Power Down Registers of the System Module before accessing any FlexRay
module register.
For more information on the FTU see the device specific technical reference manual.