Datasheet

V
CCIO
0.6*V
CCIO
0.4*V
CCIO
0
Input
t
pw
0.6*V
CCIO
0.4*V
CCIO
185
TMS570LC4357
www.ti.com SPNS195C –FEBRUARY 2014–REVISED JUNE 2016
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Peripheral Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
(1) t
c(VCLKA2)
= sample clock cycle time for FlexRay = 1 / f
(VCLKA2)
(2) t
RxAsymDelay
parameter
7.7 FlexRay Interface
The FlexRay module performs communication according to the FlexRay protocol specification v2.1. The
sample clock bitrate can be programmed to values up to 10 MBit per second. Additional bus driver (BD)
hardware is required for connection to the physical layer.
For communication on a FlexRay network, individual message buffers with up to 254 data bytes are
configurable. The message storage consists of a single-ported message RAM that holds up to 128
message buffers. All functions concerning the handling of messages are implemented in the message
handler. Those functions are the acceptance filtering, the transfer of messages between the two FlexRay
Channel Protocol Controllers and the message RAM, maintaining the transmission schedule as well as
providing message status information.
The register set of the FlexRay module can be accessed directly by the CPU through the VBUS interface.
These registers are used to control, configure and monitor the FlexRay channel protocol controllers,
message handler, global time unit, system universal control, frame/symbol processing, network
management, interrupt control, and to access the message RAM through the I/O buffer.
7.7.1 Features
The FlexRay module has the following features:
• Conformance with FlexRay protocol specification v2.1
• Data rates of up to 10 Mbps on each channel
• Up to 128 message buffers
• 8KB of message RAM for storage of for example, 128 message buffers with max. 48 byte data section
or up to 30 message buffers with 254 byte data section
• Configuration of message buffers with different payload lengths
• One configurable receive FIFO
• Each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive
FIFO
• CPU access to message buffers through input and output buffer
• FlexRay Transfer Unit (FTU) for automatic data transfer between data memory and message buffers
without CPU interaction
• Filtering for slot counter, cycle counter, and channel ID
• Maskable module interrupts
• Supports Network Management
• ECC protection on the message RAM
7.7.2 Electrical and Timing Specifications
Table 7-27. Timing Requirements for FlexRay Inputs
(1)
Parameter MIN MAX UNIT
t
pw
Input minimum pulse width to meet the FlexRay sampling
requirement
t
c(VCLKA2)
+ 2.5
(2)
ns
Figure 7-17. FlexRay Inputs