Datasheet

FlexRay Module Registers www.ti.com
26.3.2.8.6 Input Buffer Command Request Register (IBCR)
When the host writes the number of a target message buffer in the message RAM to IBRH in the input
buffer command request register, IBF host and IBF shadow are swapped. In addition the message buffer
numbers stored under IBRH and IBRS are also swapped.
With this write operation the IBSYS bit in the input buffer command request register is set to 1. The
message handler then starts to transfer the contents of IBF shadow to the message buffer in the message
RAM selected by IBRS.
While the message handler transfers the data from IBF shadow to the target message buffer in the
message RAM, the host may configure the next message in the IBF host. After the transfer between IBF
shadow and the message RAM has completed, the IBSYS bit is set back to 0 and the next transfer to the
message RAM may be started by the host by writing the respective target message buffer number to
IBRH.
If a write access to IBRH occurs while IBSYS is 1, IBSYH is set to 1. After completion of the ongoing data
transfer from IBF shadow to the message RAM, IBF host and IBF shadow are swapped, IBSYH is reset to
0. IBSYS remains set to 1, and the next transfer to the message RAM is started. In addition the message
buffer numbers stored under IBRH and IBRS are also swapped.
Any write access to an Input Buffer Register while both IBSYS and IBSYH are set will cause the error flag
IIBA in the Error Interrupt Register (EIR) to be set. In this case the Input Buffer will not be changed.
Figure 26-185 and Table 26-164 illustrate this register.
Figure 26-185. Input Buffer Command Request Register (IBCR) [offset_CC = 514h]
31 30 23 22 16
IBSYS Reserved IBRS
R-0 R-0 R-0
15 14 7 6 0
IBSYH Reserved IBRH
R-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 26-164. Input Buffer Command Request Register (IBCR) Field Descriptions
Bit Field Value Description
31 IBSYS Input buffer busy shadow. Set to 1 after writing IBRH. When the transfer between IBF shadow and
the message RAM has completed, IBSYS is set back to 0.
0 Transfer between IBF shadow and message RAM completed
1 Transfer between IBF shadow and message RAM in progress
30-23 Reserved 0 Read returns 0. Writes have no effect.
22-16 IBRS 0-7Fh Input buffer request shadow. Number of the target message buffer actually updated / lately
updated.
15 IBSYH Input buffer busy host. Set to 1 by writing IBRH while IBSYS is still 1. After the ongoing transfer
between IBF shadow and the message RAM has completed, the IBSYH is set back to 0.
0 No request pending
1 Request while transfer between IBF shadow and message RAM in progress
14-7 Reserved 0 Read returns 0. Writes have no effect.
6-0 IBRH 0-7Fh Input buffer request host. Selects the target message buffer in the Message RAM for data transfer
from Input Buffer.
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FlexRay Module SPNU563–May 2014
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