Datasheet

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26.3.2.6.3 FIFO Status Register (FSR)
The register is reset when the communication controller leaves CONFIG state, enters STARTUP state, or
by CHI command CLEAR_RAMS..
Figure 26-164 and Table 26-150 illustrate this register.
Figure 26-164. FIFO Status Register (FSR) [offset_CC = 318h]
31 16
Reserved
R-0
15 8 7 3 2 1 0
RFFL Reserved RFO RFCL RFNE
R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26-150. FIFO Status Register (FSR) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Read returns 0. Writes have no effect.
15-8 RFFL 0-7Fh Receive FIFO Fill Level. Number of FIFO buffers filled with new data not yet read by the Host.
7-7 Reserved 0 Read returns 0. Writes have no effect.
2 RFO Receive FIFO Overrun. The flag is set by the communication controller when a receive FIFO
overrun is detected. When a receive FIFO overrun occurs, the oldest message is overwritten with
the actual received message. In addition, interrupt flag RFO in the Error Interrupt Register (EIR) is
set. The flag is cleared by the next FIFO read access issued by the Host.
0 No receive FIFO overrun detected
1 A receive FIFO overrun has been detected
1 RFCL Receive FIFO Critical Level. This flag is set when the receive FIFO fill level RFFL is equal or
greater than the critical level as configured by CL in the FIFO Critical Level register (FCL). The flag
is cleared by the communication controller as soon as RFFL drops below FCL.CL. When RFCL
changes from 0 to 1, the RFCL flag in the Status Interrupt register (SIR) is set to 1, and if enabled,
an interrupt is generated.
0 Receive FIFO below critical level
1 Receive FIFO critical level reached
0 RFNE Receive FIFO Not Empty. This flag is set by the communication controller when a received valid
frame (data or null frame depending on rejection mask) was stored in the FIFO. In addition,
interrupt flag RFNE in the Status Interrupt register (SR) is set. The bit is reset after the Host has
read all message from the FIFO.
0 Receive FIFO is empty
1 Receive FIFO is not empty
1335
SPNU563–May 2014 FlexRay Module
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