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FlexRay Module Registers

Table 26-103. Status Interrupt Register (SIR) Field Descriptions (continued)

Bit Field Value Description

5 RFNE Receive FIFO not empty. This flag is set by the communication controller when a received valid

frame was stored into the empty receive FIFO. The actual state of the receive FIFO is monitored in

0 Receive FIFO is empty

1 Receive FIFO is not empty

4 RXI Receive interrupt. This flag is set by the communication controller when the payload segment of a

received valid frame was stored into the data section of a matching dedicated receive buffer and if

bit MBI of that message buffer is set to 1.

0 No data section has been updated

1 At least one data section has been updated

3 TXI Transmit interrupt. This flag is set by the communication controller after successful frame

transmission if bit MBI in the respective message buffer is set to 1.

0 No frame transmitted

1 At least one frame was transmitted successfully

2 CYCS Cycle start interrupt. This flag is set by the communication controller when a communication cycle

starts.

0 No communication cycle started

1 Communication cycle started

1 CAS Collision avoidance symbol. This flag is set by the communication controller when a CAS was

received.

0 No CAS symbol received

1 CAS symbol received

0 WST This flag is set when WSV(2:0) in the communication controller status vector register changes to a

value other than UNDEFINED.

0 Wakeup status unchanged

1 Wakeup status changed

1287

SPNU563–May 2014 FlexRay Module

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