Datasheet

FlexRay Module Registers

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Figure 26-96. Transfer to System Memory Interrupt Enable Set 4 (TSMIES4) [offset_TU = 118h]

31 16

TSMIES4(31-16)

R/S-0

15 0

TSMIES4(15-0)

R/S-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset

Table 26-82. Transfer to System Memory Interrupt Enable Set 4 (TSMIES4) Field Descriptions

Bit Field Value Description

31-0 TSMIES4(31-0) Transfer to System Memory Interrupt Enable Set 4. The register bits 0 to 31 correspond to

message buffers 96 to 127. Each bit of the register enables a potential interrupt, which occurs if the

corresponding TSMO4 bit is set:

0 No interrupt.

1 Interrupt is generated.

Figure 26-97. Transfer to System Memory Interrupt Enable Reset 4 (TSMIER4) [offset_TU = 11Ch]

31 16

TSMIER4(31-16)

R/C-0

15 0

TSMIER4(15-0)

R/C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset

Table 26-83. Transfer to System Memory Interrupt Enable Reset 4 (TSMIER4) Field Descriptions

Bit Field Description

31-0 TSMIER4(31-0) Transfer to System Memory Interrupt Enable Reset 4. The TSMIER4 register shows the identical values

to TSMIES4 if read.

1260

FlexRay Module SPNU563–May 2014

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