Datasheet

www.ti.com

FlexRay Module Registers

Figure 26-94. Transfer to System Memory Interrupt Enable Set 3 (TSMIES3) [offset_TU = 110h]

31 16

TSMIES3(31-16)

R/S-0

15 0

TSMIES3(15-0)

R/S-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset

Table 26-80. Transfer to System Memory Interrupt Enable Set 3 (TSMIES3) Field Descriptions

Bit Field Value Description

31-0 TSMIES3(31-0) Transfer to System Memory Interrupt Enable Set 3. The register bits 0 to 31 correspond to

message buffers 64 to 95. Each bit of the register enables a potential interrupt, which occurs if the

corresponding TSMO3 bit is set:

0 No interrupt.

1 Interrupt is generated.

Figure 26-95. Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3) [offset_TU = 114h]

31 16

TSMIER3(31-16)

R/C-0

15 0

TSMIER3(15-0)

R/C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset

Table 26-81. Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3) Field Descriptions

Bit Field Description

31-0 TSMIER3(31-0) Transfer to System Memory Interrupt Enable Reset 3. The TSMIER3 register shows the identical values

to TSMIES3 if read.

1259

SPNU563–May 2014 FlexRay Module

Submit Documentation Feedback