Datasheet

FlexRay Module Registers

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Figure 26-92. Transfer to System Memory Interrupt Enable Set 2 (TSMIES2) [offset_TU = 108h]

31 16

TSMIES2(31-16)

R/S-0

15 0

TSMIES2(15-0)

R/S-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset

Table 26-78. Transfer to System Memory Interrupt Enable Set 2 (TSMIES2) Field Descriptions

Bit Field Value Description

31-0 TSMIES2(31-0) Transfer to System Memory Interrupt Enable Set 2. The register bits 0 to 31 correspond to

message buffers 32 to 63. Each bit of the register enables a potential interrupt, which occurs if the

corresponding TSMO2 bit is set:

0 No interrupt.

1 Interrupt is generated.

Figure 26-93. Transfer to System Memory Interrupt Enable Reset 2 (TSMIER2) [offset_TU = 10Ch]

31 16

TSMIER2(31-16)

RC-0

15 0

TSMIER2(15-0)

R/C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset

Table 26-79. Transfer to System Memory Interrupt Enable Reset 2 (TSMIER2) Field Descriptions

Bit Field Description

31-0 TSMIER2(31-0) Transfer to System Memory Interrupt Enable Reset 2. The TSMIER2 register shows the identical values

to TSMIES2 if read.

1258

FlexRay Module SPNU563–May 2014

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