Datasheet

www.ti.com FlexRay Module Registers
26.3.1.23 Transfer to System Memory Interrupt Enable Set/Reset (TSMIES[1-4]/TSMIER[1-4])
The Transfer to System Memory Interrupt Enable registers enable the interrupt generation on interrupt line
TU_Int0, after a transfer to the system memory occurred (flagged in TSMO). Four 32-bit Registers reflect
all 128 MB’s.
The bits are set by writing 1 to TSMIESx and reset by writing 1 to TSMIERx. Writing a 0 has no effect.
Reading from both addresses will result in the same value.
Figure 26-90. Transfer to System Memory Interrupt Enable Set 1 (TSMIES1) [offset_TU = 100h]
31 16
TSMIES1(31-16)
R/S-0
15 0
TSMIES1(15-0)
R/S-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset
Table 26-76. Transfer to System Memory Interrupt Enable Set 1 (TSMIES1) Field Descriptions
Bit Field Value Description
31-0 TTSMIES1(31-0) Transfer to System Memory Interrupt Enable Set 1. The register bits 0 to 31 correspond to
message buffers 0 to 31. Each bit of the register enables a potential interrupt, which occurs if the
corresponding TSMO1 bit is set:
0 No interrupt.
1 Interrupt is generated.
Figure 26-91. Transfer to System Memory Interrupt Enable Reset 1 (TSMIER1) [offset_TU = 104h]
31 16
TSMIER1(31-16)
R/C-0
15 0
TSMIER1(15-0)
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset
Table 26-77. Transfer to System Memory Interrupt Enable Reset 1 (TSMIER1) Field Descriptions
Bit Field Description
31-0 TSMIER1(31-0) Transfer to System Memory Interrupt Enable Reset 1. The TSMIER1 register shows the identical values
to TSMIES1 if read.
1257
SPNU563–May 2014 FlexRay Module
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