Datasheet
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FlexRay Module Registers
26.3.1.18 Transfer Error Interrupt Enable Set/Reset (TEIRES/R)
The Transfer Error Interrupt Enable Set controls the interrupt activation of interrupt line TU_Int1. An
interrupt is generated if both the interrupt flag in TEIF and the corresponding bit in TEIRES are set.
Exceptions are the memory protection violation (MPV) and the ECC (PE) error, which are related to
nonmaskable interrupts, and therefore are not part of the TEIRS/R registers. Those errors have private
error lines (TU_MPV_err and TU_UCT_err), which can be connected to the Vectored Interrupt Module
(VIM) and/or the Error Signaling Module (ESM). Refer to the specific device data sheet for more details
about the signal hookup.
A Transfer Error Interrupt is enabled by writing 1 to TEIRES register and disabled by writing 1 to TIERER
register. Writing of 0 has no effect. Reading from both addresses will result in the same value.
Figure 26-56. Transfer Error Interrupt Enable Set (TEIRES) [offset_TU = 78h]
31 16
Reserved
R-0
15 11 10 8 7 6 4 3 2 1 0
Reserved RSTAT RSVD WSTAT Reserved TNRE FACE
R-0 R/S-0 R-0 R/S-0 R-0 R/S-0 R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 26-42. Transfer Error Interrupt Enable Set (TEIRES)
Bit Field Value Description
31-11 Reserved 0 Reads return 0. Writes have no effect.
10-8 RSTATE Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors).
0 Interrupt generation on VBUS read transfer error disabled.
7h Interrupt generation on VBUS read transfer error enabled.
Note: Any value different from 111 does not guarantee the interrupt error generation of all possible
VBUS read errors.
7 Reserved 0 Reads return 0. Writes have no effect.
6-4 WSTATE Write Error Interrupt Generation (interrupt generation on VBUS write transfer errors).
0 Interrupt generation on VBUS write transfer error disabled.
7h Interrupt generation on VBUS write transfer error enabled.
Note: Any value different from 111 does not guarantee the interrupt error generation of all possible
VBUS read errors.
3-2 Reserved 0 Reads return 0. Writes have no effect.
1 TNRE Transfer Not Ready Enable.
0 TNR interrupt disabled.
1 TNR interrupt enabled.
0 FACE Forbidden Access Enable.
0 FAC interrupt disabled.
1 FAC interrupt enabled.
1239
SPNU563–May 2014 FlexRay Module
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