Datasheet

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26.3.1.13 Transfer to Communication Controller Occurred (TCCO[1-4])
The Transfer to Communication Controller Occurred reflects the message buffer transfer status for a
VBUSP master transfer transaction from the system memory. Four 32-bit registers reflect all possible 128
message buffers.
NOTE: Writing 1 will clear a bit. Writing 0 will leave a bit unchanged.
Figure 26-48. Transfer to Communication Controller Occurred 1 (TCCO1) [offset_TU = 50h]
31 16
TCCO1(31-16)
R/W1C-0
15 0
TCCO1(15-0)
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 26-34. (Transfer to Communication Controller Occurred 1 (TCCO1) Field Descriptions
Bit Field Value Description
31-0 TCCO1(31-0) Transfer to Communication Controller Occurred Register 1.
The register bits 0 to 31 correspond to message buffers 0 to 31. Each bit of the register reflects a
finished message buffer transfer from the system memory.
0 No transfer occurred.
1 Transfer occurred.
Figure 26-49. Transfer to Communication Controller Occurred 2 (TCCO2) [offset_TU = 54h]
31 16
TCCO2(31-16)
R/W1C-0
15 0
TCCO2(15-0)
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 26-35. (Transfer to Communication Controller Occurred 2 (TCCO2) Field Descriptions
Bit Field Value Description
31-0 TCCO2(31-0) Transfer to Communication Controller Occurred Register 2.
The register bits 0 to 31 correspond to message buffers 32 to 63. Each bit of the register reflects a
finished message buffer transfer from the system memory.
0 No transfer occurred.
1 Transfer occurred.
1232
FlexRay Module SPNU563–May 2014
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