Datasheet

www.ti.com FlexRay Module Registers
Figure 26-46. Transfer to System Memory Occurred 3 (TSMO3) [offset_TU = 48h]
31 16
TSMO3(31-16)
R/W1C-0
15 0
TSMO3(15-0)
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 26-32. Transfer to System Memory Occurred 3 (TSMO3) Field Descriptions
Bit Field Value Description
31-0 TSMO3(31-0) Transfer to System Memory Occurred Register 3.
The register bits 0 to 31 correspond to message buffers 64 to 95. Each bit of the register reflects a
finished message buffer transfer to the system memory.
0 No transfer occurred.
1 Transfer occurred.
Figure 26-47. Transfer to System Memory Occurred 4 (TSMO4) [offset_TU = 4Ch]
31 16
TSMO4(31-16)
R/W1C-0
15 0
TSMO4(15-0)
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 26-33. Transfer to System Memory Occurred 4 (TSMO4) Field Descriptions
Bit Field Value Description
31-0 TSMO4(31-0) Transfer to System Memory Occurred Register 4.
The register bits 0 to 31 correspond to message buffers 96 to 127. Each bit of the register reflects a
finished message buffer transfer to the system memory.
0 No transfer occurred.
1 Transfer occurred.
1231
SPNU563–May 2014 FlexRay Module
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