Datasheet
Bit
Word
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
M
B
I
T
X
M
P
P
I
T
C
F
G
C
H
B
C
H
A
Cycle Code Frame ID
1
Payload Length
Received
Payload Length
Configured
Tx Buffer: Header CRC Configured
Rx Buffer: Header CRC Received
2
R
E
S
P
P
I
N
F
I
S
Y
N
S
F
I
R
C
I
Receive
Cycle Count
Data Pointer
3
R
E
S
S
P
P
I
S
N
F
I
S
S
Y
N
S
S
F
I
S
R
C
I
S
Cycle Count Status
F
T
B
F
T
A
M
L
S
T
E
S
B
E
S
A
T
C
I
B
T
C
I
A
S
V
O
B
S
V
O
A
C
E
O
B
C
E
O
A
S
E
O
B
S
E
O
A
V
F
R
B
V
F
R
A
: :
: :
Frame Configuration
Filter Configuration
Message Buffer Control
Message RAM Configuration
Updated from received Frame
Message Buffer Status
unused
Module Operation
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Payload length received (PLR(6-0)), receive cycle count (RCC(5-0)), Received on Channel Indication
(RCI), Startup Frame Indication bit (SFI), sync bit (SYN), null frame indication bit (NFI), payload preamble
indication bit (PPI), and reserved bit (RES) are only updated from received valid data frames only.
Header word 3 of each configured message buffer holds the corresponding message buffer status MBS.
Figure 26-24. Header Section of Message Buffer in Message RAM
Header 1 (Word 0)
Write access through WRHS1, read access through RDHS1:
• Frame ID- Slot counter filtering configuration
• Cycle Code- Cycle counter filtering configuration
• CHA, CHB- Channel filtering configuration
• CFG- Message buffer configuration: receive / transmit
• PPIT- Payload Preamble Indicator Transmit
• TXM- Transmit mode configuration: single-shot / continuous
• MBI- Message buffer receive / transmit interrupt enable
1202
FlexRay Module SPNU563–May 2014
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