Datasheet

113
TMS570LC4357
www.ti.com SPNS195C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
Table 6-36. EMIF Asynchronous Memory Switching Characteristics
(1)(2)(3)
(continued)
NO. PARAMETER MIN TYP MAX UNIT
16 t
su(EMCEL-EMWEL)
Output setup time, EMIF_nCS[4:2] low to
EMIF_nWE low (SS = 0)
(WS)*E -3 (WS)*E (WS)*E + 3 ns
Output setup time, EMIF_nCS[4:2] low to
EMIF_nWE low (SS = 1)
–3 0 3 ns
17 t
h(EMWEH-EMCEH)
Output hold time, EMIF_nWE high to
EMIF_nCS[4:2] high (SS = 0)
(WH)*E-3 (WH)*E (WH)*E+3 ns
Output hold time, EMIF_nWE high to
EMIF_CS[4:2] high (SS = 1)
–3 0 3 ns
18 t
su(EMDQMV-EMWEL)
Output setup time, EMIF_nDQM[1:0] valid to
EMIF_nWE low
(WS)*E-3 (WS)*E (WS)*E+3 ns
19 t
h(EMWEH-EMDQMIV)
Output hold time, EMIF_nWE high to
EMIF_nDQM[1:0] invalid
(WH)*E-3 (WH)*E (WH)*E+3 ns
20 t
su(EMBAV-EMWEL)
Output setup time, EMIF_BA[1:0] valid to
EMIF_nWE low
(WS)*E-3 (WS)*E (WS)*E+3 ns
21 t
h(EMWEH-EMBAIV)
Output hold time, EMIF_nWE high to
EMIF_BA[1:0] invalid
(WH)*E-3 (WH)*E (WH)*E+3 ns
22 t
su(EMAV-EMWEL)
Output setup time, EMIF_ADDR[21:0] valid to
EMIF_nWE low
(WS)*E-3 (WS)*E (WS)*E+3 ns
23 t
h(EMWEH-EMAIV)
Output hold time, EMIF_nWE high to
EMIF_ADDR[21:0] invalid
(WH)*E-3 (WH)*E (WH)*E+3 ns
24 t
w(EMWEL)
EMIF_nWE active low width (EW = 0) (WST)*E-3 (WST)*E (WST)*E+3 ns
EMIF_nWE active low width (EW = 1) (WST+EWC) *E-3 (WST+EWC)*E (WST+EWC) *E+3 ns
25 t
d(EMWAITH-EMWEH)
Delay time from EMIF_nWAIT deasserted to
EMIF_nWE high
3E+3 4E 4E+14 ns
26 t
su(EMDV-EMWEL)
Output setup time, EMIF_DATA[15:0] valid to
EMIF_nWE low
(WS)*E-3 (WS)*E (WS)*E+3 ns
27 t
h(EMWEH-EMDIV)
Output hold time, EMIF_nWE high to
EMIF_DATA[15:0] invalid
(WH)*E-3 (WH)*E (WH)*E+3 ns