Datasheet

112
TMS570LC4357
SPNS195C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Table 6-35. EMIF Asynchronous Memory Timing Requirements
(1)
(continued)
NO. MIN NOM MAX UNIT
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure 6-12 and Figure 6-14 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
2 t
w(EM_WAIT)
Pulse duration, EMIFnWAIT assertion and deassertion 2E ns
Reads
12 t
su(EMDV-EMOEH)
Setup time, EMIFDATA[15:0] valid before EMIFnOE high 11 ns
13 t
h(EMOEH-EMDIV)
Hold time, EMIFDATA[15:0] valid after EMIFnOE high 0.5 ns
14 t
su(EMOEL-EMWAIT)
Setup Time, EMIFnWAIT asserted before end of Strobe Phase
(2)
4E+14 ns
Writes
28 t
su(EMWEL-EMWAIT)
Setup Time, EMIFnWAIT asserted before end of Strobe Phase
(2)
4E+14 ns
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait
Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1],
WST[64–1], WH[8–1], and MEWC[1–256]. See the EMIF chapter of the TRM SPNU563 for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note
that the maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See
the EMIF chapter of the TRM SPNU563 for more information.
Table 6-36. EMIF Asynchronous Memory Switching Characteristics
(1)(2)(3)
NO. PARAMETER MIN TYP MAX UNIT
Reads and Writes
1 t
d(TURNAROUND)
Turn around time (TA)*E -3 (TA)*E (TA)*E + 3 ns
Reads
3 t
c(EMRCYCLE)
EMIF read cycle time (EW = 0) (RS+RST+RH)*E-3 (RS+RST+RH)*E (RS+RST+RH)*E + 3 ns
EMIF read cycle time (EW = 1)
(RS+RST+RH+
EWC)*E -3
(RS+RST+RH+
EWC)*E
(RS+RST+RH+
EWC)*E + 3
ns
4 t
su(EMCEL-EMOEL)
Output setup time, EMIF_nCS[4:2] low to
EMIF_nOE low (SS = 0)
(RS)*E-3 (RS)*E (RS)*E+3 ns
Output setup time, EMIFnCS[4:2] low to
EMIF_nOE low (SS = 1)
–3 0 3 ns
5 t
h(EMOEH-EMCEH)
Output hold time, EMIF_nOE high to
EMIF_nCS[4:2] high (SS = 0)
(RH)*E -4 (RH)*E (RH)*E + 3 ns
Output hold time, EMIF_nOE high to
EMIF_nCS[4:2] high (SS = 1)
–4 0 3 ns
6 t
su(EMBAV-EMOEL)
Output setup time, EMIF_BA[1:0] valid to
EMIF_nOE low
(RS)*E-3 (RS)*E (RS)*E+3 ns
7 t
h(EMOEH-EMBAIV)
Output hold time, EMIF_nOE high to
EMIF_BA[1:0] invalid
(RH)*E-4 (RH)*E (RH)*E+3 ns
8 t
su(EMBAV-EMOEL)
Output setup time, EMIF_ADDR[21:0] valid to
EMIF_nOE low
(RS)*E-3 (RS)*E (RS)*E+3 ns
9 t
h(EMOEH-EMAIV)
Output hold time, EMIF_nOE high to
EMIF_ADDR[21:0] invalid
(RH)*E-4 (RH)*E (RH)*E+3 ns
10 t
w(EMOEL)
EMIF_nOE active low width (EW = 0) (RST)*E-3 (RST)*E (RST)*E+3 ns
EMIF_nOE active low width (EW = 1) (RST+EWC) *E-3 (RST+EWC)*E (RST+EWC) *E+3 ns
11 t
d(EMWAITH-EMOEH)
Delay time from EMIF_nWAIT deasserted to
EMIF_nOE high
3E-3 4E 4E+5 ns
29 t
su(EMDQMV-EMOEL)
Output setup time, EMIF_nDQM[1:0] valid to
EMIF_nOE low
(RS)*E-5 (RS)*E (RS)*E+3 ns
30 t
h(EMOEH-EMDQMIV)
Output hold time, EMIF_nOE high to
EMIF_nDQM[1:0] invalid
(RH)*E-4 (RH)*E (RH)*E+5 ns
Writes
15 t
c(EMWCYCLE)
EMIF write cycle time (EW = 0) (WS+WST+WH)* E-3 (WS+WST+WH)*E (WS+WST+WH)* E+3 ns
EMIF write cycle time (EW = 1)
(WS+WST+WH+
EWC)*E -3
(WS+WST+WH+
EWC)*E
(WS+WST+WH+
EWC)*E + 3
ns