Datasheet

EMIF_nCS[3:2]
25
Asserted
2
2
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
EMIF_nWE
EMIF_WAIT
SETUP
Extended Due to EMIF_WAIT
28
Deasserted
STROBE STROBE HOLD
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_nWE
EMIF_DATA[15:0]
EMIF_nOE
15
1
16
18
20
22
24
17
19
21
23
26
27
EMIF_nDQM[1:0]
111
TMS570LC4357
www.ti.com SPNS195C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
(1) E = EMIF_CLK period in ns.
6.14.2.2 Write Timing (Asynchronous RAM)
Figure 6-13. Asynchronous Memory Write Timing
Figure 6-14. EMIFnWAIT Write Timing Requirements
6.14.2.3 EMIF Asynchronous Memory Timing
Table 6-35. EMIF Asynchronous Memory Timing Requirements
(1)
NO. MIN NOM MAX UNIT
Reads and Writes