Datasheet

EMIF_nCS[3:2]
11
Asserted Deasserted
2
2
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
EMIF_nOE
EMIF_WAIT
SETUP
Extended Due to EMIF_WAIT
STROBE HOLD
14
STROBE
EMIF_nCS[3:2]
EMIF_BA[1:0]
13
12
EMIF_ADDR[21:0]
EMIF_nOE
EMIF_DATA[15:0]
EMIF_nWE
10
5
9
7
4
8
6
3
1
EMIF_nDQM[1:0]
30
29
110
TMS570LC4357
SPNS195C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
6.14.2 Electrical and Timing Specifications
6.14.2.1 Read Timing (Asynchronous RAM)
Figure 6-11. Asynchronous Memory Read Timing
Figure 6-12. EMIFnWAIT Read Timing Requirements