Datasheet

106
TMS570LC4357
SPNS195C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Table 6-33. PBIST RAM Grouping (continued)
MEMORY
RAM
GROUP
TEST CLOCK RGS RDS
MEM
TYPE
NO.
BANKS
TEST PATTERN
(ALGORITHM)
TRIPLE
READ
SLOW READ
TRIPLE
READ
FAST READ
March 13N
(1)
TWO PORT
(cycles)
March 13N
(1)
SINGLE
PORT
(cycles)
ALGO MASK
0x1
ALGO MASK
0x2
ALGO MASK
0x4
ALGO MASK
0x8
L2RAMW 29 GCM_HCLK 7
1 SP 4
532580
6 SP 4
L2RAMW 30 GCM_HCLK 32
1 SP 4
1597740
6 SP 4
11 SP 4
16 SP 4
21 SP 4
26 SP 4
R5_ICACHE 31 GCM_GCLK1 40
1 SP 4
166600
6 SP 4
11 SP 4
16 SP 4
R5_DCACHE 32 GCM_GCLK1 41
1 SP 4
299820
6 SP 4
11 SP 4
16 SP 4
21 SP 4
26 SP 4
Reserved 33 GCM_GCLK2 43
1 SP 4
166600
6 SP 4
11 SP 4
16 SP 4
Reserved 34 GCM_GCLK2 44
1 SP 4
299820
6 SP 4
11 SP 4
16 SP 4
21 SP 4
26 SP 4
FRAY_TRBUF_MSG
RAM
35 GCM_VCLKP 26 9..11 SP 3 149910
CPGMAC_CPPI 36 GCM_VCLK3 27 7 SP 1 133170
R5_DCACHE_Dirty 37 GCM_GCLK1 42 2 SP 1 16690
Reserved 38 - - - - - -
Several memory testing algorithms are stored in the PBIST ROM. However, TI only recommends the
March13N algorithm for application testing of RAM.
The PBIST ROM clock frequency is limited to the maximum frequency of 82.5 MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV
field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.