Datasheet

SPICLK
(clock polarity=0)
SPISIMO
SPICSn
Master Out Data Is Valid
9
SPICLK
(clock polarity=1)
SPIENAn
10
Write to buffer
11
8
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Data Valid
Master In Data
Must Be Valid
Master Out Data Is Valid
3
2
1
5
4
7
6
TMS570LS0432
TMS570LS0332
www.ti.com SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013
Figure 5-8. SPI Master Mode External Timing (CLOCK PHASE = 1)
Figure 5-9. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
Copyright © 2012–2013, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 87
Submit Documentation Feedback
Product Folder Links: TMS570LS0432 TMS570LS0332