Datasheet

TMS570LS0432
TMS570LS0332
SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013 www.ti.com
Table 5-7. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions
Parameter Description/Conditions MIN Type MAX Unit
CR Conversion range AD
REFHI
- AD
REFLO
3 3.6 V
over which
specified
accuracy is
maintained
Z
SET
Offset Error Difference between the first ideal 10-bit With ADC 1 LSB
transition (from code 000h to 001h) mode Calibration
and the actual transition
Without ADC 2 LSB
Calibration
12-bit With ADC 2 LSB
mode Calibration
Without ADC 4 LSB
Calibration
F
SET
Gain Error Difference between the last ideal 10-bit mode 2 LSB
transition (from code FFEh to FFFh)
12-bit mode 3 LSB
and the actual transition minus offset.
E
DNL
Differential Difference between the actual step 10-bit mode ± 1.5 LSB
nonlinearity error width and the ideal value. (See
12-bit mode ± 2 LSB
Figure 5-2)
E
INL
Integral Maximum deviation from the best 10-bit mode ± 2 LSB
nonlinearity error straight line through the MibADC.
12-bit mode ± 2 LSB
MibADC transfer characteristics,
excluding the quantization error. (See
Figure 5-3)
E
TOT
Total unadjusted Maximum value of the difference 10-bit With ADC ± 2 LSB
error between an analog value and the mode Calibration
ideal midstep value. (See Figure 5-4)
Without ADC ± 4 LSB
Calibration
12-bit With ADC ± 4 LSB
mode Calibration
Without ADC ± 7 LSB
Calibration
72 Peripheral Information and Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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