Datasheet
V
S1
On-State
Leakage
Off-State
Leakages
V
S2
V
S24
23*I
AIL
I
AIL
I
AIL
R
ext
R
ext
R
ext
P
in
S
mux
R
mux
P
in
S
mux
R
mux
P
in
S
mux
R
mux
S
samp
R
samp
C
samp
C
ext
I
AIL
I
AIL
I
AIL
I
AIL
C
mux
C
ext
C
ext
TMS570LS0432
TMS570LS0332
www.ti.com
SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013
Figure 5-1. MibADC Input Equivalent Circuit
Table 5-6. MibADC Timing Specifications
Parameter MIN NOM MAX Unit
t
c(ADCLK)
(1)
Cycle time, MibADC clock 33 ns
t
d(SH)
(2)
Delay time, sample and hold 200 ns
time
t
d(PU-ADV)
Delay time from ADC power on 1 µs
until first input can be sampled
12-bit mode
t
d(C)
Delay time, conversion time 400 ns
t
d(SHC)
(3)
Delay time, total sample/hold 600 ns
and conversion time
10-bit mode
t
d(C)
Delay time, conversion time 330 ns
t
d(SHC)
(4)
Delay time, total sample/hold 530 ns
and conversion time
(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits
4:0.
(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each
conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as
well as the ADC’s internal impedance.
(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the
prescale settings.
(4) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the
prescale settings.
Copyright © 2012–2013, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 71
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