Datasheet

TMS570LS0432
TMS570LS0332
www.ti.com SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the technical changes made to the initial revision of the
device-specific data manual to make it an A revision.
Document Revision History
Section Change From To
Section 3.1 Increased absolute max voltage V
CCIO
and Input Voltage 4.1 V 4.6 V
Section 3.2 Added maximum 3.3V supply voltage slew rate 1 V/µs
Added table of control bits for programmable 8 mA / 2 mA
Table 3-3
buffers
Section 3.4 Revised wait state requirements
Added that after reset, flash bank 7 reads have two data wait-
Section 3.3
states
15 mA, 34 mA, 15
Section 3.5 Combined I
CCIO
, I
CCP
and I
CCAD
45 mA
mA,
Section 3.5 Added derating factors for Icc current
Section 3.6 V
OH
, I
OH
= 50 µA, standard output mode V
CCIO
-0.2 V
CCIO
-0.3
Section 3.6 Input clamp current -2 mA -3.5 mA
Section 3.6 Input clamp current 2 mA 3.5 mA
Added table note warning not to do byte or halfword writes to
Table 3-3
SPI2PC9[32.16]
Table 4-21 Corrected size of bank 7 and programming times 64KB 16KB
Table 4-1 Vmon Vcc high 1.0 V 1.13 V
Table 4-6 Corrected nRST timings 8 t
c(VCLK)
32 t
c(VCLK)
Table 5-5 Updated ADC leakage table
Section 5.7.4
Updated SPI timings
Section 5.7.5
Table 6-2 Updated Die-ID register
Section 6.4 Added section for module certifications
Copyright © 2012–2013, Texas Instruments Incorporated Contents 7
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