Datasheet

TRST
TMS
TCK
TDI
TDO
RTCK
ICEPICK_C
BoundaryScan
BSR/BSDL
BoundaryScanI/F
SecondaryTap0
DAP
Debug APB
Debug
ROM1
APBslave
Cortex
R4
TestTap0
eFuseFarm
SecondaryTap2
AJSM
TMS570LS0432
TMS570LS0332
SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013 www.ti.com
4.20 Debug Subsystem
4.20.1 Block Diagram
The device contains an ICEPICK module to allow JTAG access to the scan chains.
Figure 4-14. ZWT Debug Subsystem Block Diagram
4.20.2 Debug Components Memory Map
Table 4-28. Debug Components Memory Map
FRAME ADDRESS RANGE RESPONSE FOR ACCESS TO
FRAME CHIP FRAME ACTUA
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT SIZE L SIZE
START END
FRAME
CoreSight Debug Reads return zeros, writes have no
CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB
ROM effect
Reads return zeros, writes have no
Cortex-R4 Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB
effect
4.20.3 JTAG Identification Code
The JTAG ID code for this device is 0x0B97102F. This is the same as the device ICEPick Identification
Code.
4.20.4 Debug ROM
The Debug ROM stores the location of the components on the Debug APB bus:
Table 4-29. Debug ROM table
ADDRESS DESCRIPTION VALUE
0x000 pointer to Cortex-R4 0x0000 1003
0x001 Reserved 0x0000 2002
0x002 Reserved 0x0000 3002
0x003 Reserved 0x0000 4002
0x004 end of table 0x0000 0000
64 System Information and Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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