Datasheet
TMS570LS0432
TMS570LS0332
SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013
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4.17 Error Signaling Module
The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller.
The error condition is handled based on a fixed severity level assigned to it. Any severe error condition
can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used
as an indicator to an external monitor circuit to put the system into a safe state.
4.17.1 Features
The features of the Error Signaling Module are:
• 128 interrupt/error channels are supported, divided into 3 different groups
– 64 channels with maskable interrupt and configurable error pin behavior
– 32 error channels with non-maskable interrupt and predefined error pin behavior
– 32 channels with predefined error pin behavior only
• Error pin to signal severe device failure
• Configurable timebase for error signal
• Error forcing capability
4.17.2 ESM Channel Assignments
The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order
of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest
severity. The device response to each error is determined by the severity group it is connected to.
Table 4-26 shows the channel assignment for each group.
Table 4-25. ESM Groups
ERROR GROUP INTERRUPT CHARACTERISTICS INFLUENCE ON ERROR PIN
Group1 maskable, low or high priority configurable
Group2 non-maskable, high priority fixed
Group3 no interrupt generated fixed
Table 4-26. ESM Channel Assignments
ERROR SOURCES GROUP CHANNELS
Reserved Group1 0
Reserved Group1 1
Reserved Group1 2
Reserved Group1 3
Reserved Group1 4
Reserved Group1 5
FMC - correctable error: bus1 and bus2 interfaces (does not include accesses to Group1 6
EEPROM bank)
N2HET - parity Group1 7
HTU - parity Group1 8
HTU - MPU Group1 9
PLL - Slip Group1 10
Clock Monitor - interrupt Group1 11
Reserved Group1 12
Reserved Group1 13
Reserved Group1 14
VIM RAM - parity Group1 15
Reserved Group1 16
MibSPI1 - parity Group1 17
58 System Information and Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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