Datasheet

310
Compare
control
INTy
Compare
Update
compare
Fromcounter
block0
Fromcounter
block1
RTIUDCPy
RTICOMPy
310
=
+
TMS570LS0432
TMS570LS0332
www.ti.com SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013
Figure 4-13. Compare Block Diagram
4.16.3 Clock Source Options
The RTI module uses the RTICLK clock domain for generating the RTI time bases.
The application can select the clock source for the RTICLK by configuring the RCLKSRC register in the
System module at address 0xFFFFFF50. The default source for RTICLK is VCLK.
For more information on clock sources refer to Table 4-8 and Table 4-12.
Copyright © 2012–2013, Texas Instruments Incorporated System Information and Electrical Specifications 57
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