Datasheet

TMS570LS0432
TMS570LS0332
SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013 www.ti.com
4.14 On-Chip SRAM Initialization and Testing
4.14.1 On-Chip SRAM Self-Test Using PBIST
4.14.1.1 Features
• Extensive instruction set to support various memory test algorithms
• ROM-based algorithms allow application to run TI production-level memory tests
• Independent testing of all on-chip SRAM
4.14.1.2 PBIST RAM Groups
Table 4-22. PBIST RAM Grouping
Test Pattern (Algorithm)
March 13N
(1)
March 13N
(1)
triple read triple read
two port single port
Memory RAM Group Test Clock MEM Type slow read fast read
(cycles) (cycles)
ALGO MASK ALGO MASK ALGO MASK ALGO MASK
0x1 0x2 0x4 0x8
PBIST_ROM 1 ROM CLK ROM X X
STC_ROM 2 ROM CLK ROM X X
DCAN1 3 VCLK Dual Port 12720
DCAN2 4 VCLK Dual Port 6480
ESRAM1 6 HCLK Single Port 133160
MIBSPI1 7 VCLK Dual Port 33440
VIM 10 VCLK Dual Port 12560
MIBADC 11 VCLK Dual Port 4200
N2HET1 13 VCLK Dual Port 25440
HTU1 14 VCLK Dual Port 6480
(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for
application testing.
The PBIST ROM clock can be divided down from HCLK. The divider is selected by programming the
ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
52 System Information and Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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