Datasheet

TMS570LS0432
TMS570LS0332
www.ti.com SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013
4.9 Flash Memory
4.9.1 Flash Memory Configuration
Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a
customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense
amplifiers, and control logic.
Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical
construction constraints.
Flash Pump: A charge pump which generates all the voltages required for reading, programming, or
erasing the flash banks.
Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.
Table 4-19. Flash Memory Banks and Sectors
Memory Arrays (or Banks)
(1)
Block Sector Segment Low Address High Address
No. No.
BANK0 (384kBytes) 0 0 8K Bytes 0x0000_0000 0x0000_1FFF
1 8K Bytes 0x0000_2000 0x0000_3FFF
2 8K Bytes 0x0000_4000 0x0000_5FFF
3 8K Bytes 0x0000_6000 0x0000_7FFF
4 8K Bytes 0x0000_8000 0x0000_9FFF
5 8K Bytes 0x0000_A000 0x0000_BFFF
6 8K Bytes 0x0000_C000 0x0000_DFFF
7 8K Bytes 0x0000_E000 0x0000_FFFF
8 8K Bytes 0x0001_0000 0x0001_1FFF
9 8K Bytes 0x0001_2000 0x0001_3FFF
10 8K Bytes 0x0001_4000 0x0001_5FFF
11 8K Bytes 0x0001_6000 0x0001_7FFF
12 32K Bytes 0x0001_8000 0x0001_FFFF
1 13 128K Bytes 0x0002_0000 0x0003_FFFF
2 14
(2)
128K Bytes 0x0004_0000 0x0005_FFFF
BANK7 (16kBytes) for EEPROM 0 0 4K Bytes 0xF020_0000 0xF020_0FFF
emulation
(3)(4)
1 1 4K Bytes 0xF020_1000 0xF020_1FFF
2 2 4K Bytes 0xF020_2000 0xF020_2FFF
3 3 4K Bytes 0xF020_3000 0xF020_3FFF
(1) The Flash banks are 144-bit wide bank with ECC support.
(2) Sector 14 is not accessible or included in the TMS570LS0332 configuration.
(3) Flash bank7 is an FLEE bank and can be programmed while executing code from flash bank0.
(4) Code execution is not allowed from flash bank7.
4.9.2 Main Features of Flash Module
• Support for multiple flash banks for program and/or data storage
• Simultaneous read access on a bank while performing program or erase operation on any other bank
• Integrated state machines to automate flash erase and program operations
• Software interface for flash program and erase operations
• Pipelined mode operation to improve instruction access interface bandwidth
• Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4 CPU
– Error address is captured for host system debugging
• Support for a rich set of diagnostic features
Copyright © 2012–2013, Texas Instruments Incorporated System Information and Electrical Specifications 47
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