Datasheet

TMS570LS0432
TMS570LS0332
SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013 www.ti.com
4.8.3 Master/Slave Access Privileges
The table below lists the access permissions for each bus master on the device. A bus master is a module
that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
Table 4-18. Master / Slave Access Matrix
MASTERS ACCESS MODE SLAVES ON MAIN SCR
Flash Module Bus2 Non-CPU Accesses CRC Peripheral Control
Interface: to Program Flash Registers, All
OTP, ECC, EEPROM and CPU Data RAM Peripheral
Bank Memories, And All
System Module
Control Registers
And Memories
CPU READ User/Privilege Yes Yes Yes Yes
CPU WRITE User/Privilege No Yes Yes Yes
HTU Privilege No Yes Yes Yes
46 System Information and Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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