Datasheet

TMS570LS0432
TMS570LS0332
www.ti.com SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013
4.5.3 Clock Test Mode
The TMS570 platform architecture defines a special mode that allows various clock signals to be brought
out on to the ECLK pin and N2HET[2] device outputs. This mode is called the Clock Test mode. It is very
useful for debugging purposes and can be configured via the CLKTEST register in the system module.
Table 4-13. Clock Test Mode Options
CLKTEST[3-0] SIGNAL ON ECLK CLKTEST[11-8] SIGNAL ON N2HET[2]
0000 Oscillator 0000 Oscillator Valid Status
Main PLL free-running clock output
0001 0001 Main PLL Valid status
(PLLCLK)
0010 Reserved 0010 Reserved
0011 Reserved 0011 Reserved
0100 CLK80K 0100 Reserved
0101 CLK10M 0101 CLK10M Valid status
0110 Reserved 0110 Reserved
0111 Reserved 0111 Reserved
1000 GCLK 1000 CLK80K
1001 RTI Base 1001 Oscillator Valid status
1010 Reserved 1010 Oscillator Valid status
1011 VCLKA1 1011 Oscillator Valid status
1100 Reserved 1100 Oscillator Valid status
1101 Reserved 1101 Oscillator Valid status
1110 Reserved 1110 Oscillator Valid status
1111 Flash HD Pump Oscillator 1111 Oscillator Valid status
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