Datasheet

VCLK
/1,2,..1024
Phase_seg2
CANBaudRate
Phase_seg1
DCAN1,2
AVCLK1
/1,2,..256
SPIx,MibSPIx
/2,3..2
24
LIN
SPI
LIN
/1,2..32
MibADC
ADCLK
/1,2..65536
ExternalClock
ECLK
VCLK2
N2HET
Prop_seg
HRP
/1..64
LRP
/2
0
..2
7
Loop
ResolutionClock
High
BaudRate
BaudRate
HET TU
VCLK2
HCLK(toSYSTEM)
GCLK,GCLK2(toCPU)
GCM
VCLK(toSystemand
VCLK2(toN2HET)
AVCLK1(toDCAN1,2)
1
4
5
VCLK
0
/1..16
/1..16
RTICLK(toRTI+DWWD)
/1,2,4,or8
1
0
4
5
VCLK
OSCIN
LowPower
Oscillator
10MHz
80kHz
FMzPLL
1
0
4
5
/1..64
X1..256 /1..8 /1..32
* Thefrequencyatthisnode mustnot
exceedthemaximumHCLKfrequency.
*
3
3
PeripheralModules)
eQEP
3
EXTCLKIN
CDDISx.9
TMS570LS0432
TMS570LS0332
SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013 www.ti.com
4.5.2.2 Mapping of Clock Domains to Device Modules
Each clock domain has a dedicated functionality as shown in the figure below.
Figure 4-7. Device Clock Domains
36 System Information and Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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