Datasheet

TMS570LS0432
TMS570LS0332
www.ti.com SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013
Table 4-12. Clock Domain Descriptions (continued)
Clock Domain Name Default Clock Clock Source Description
Source Selection Register
VCLK OSCIN GHVSRC
• Divided down from HCLK
• Can be HCLK/1, HCLK/2, ... or HCLK/16
• Is disabled separately from HCLK via the CDDISx registers bit 2
• Can be disabled separately for eQEP using CDDISx registers
bit 9
VCLK2 OSCIN GHVSRC
• Divided down from HCLK
• Can be HCLK/1, HCLK/2, ... or HCLK/16
• Frequency must be an integer multiple of VCLK frequency
• Is disabled separately from HCLK via the CDDISx registers bit 3
VCLKA1 VCLK VCLKASRC
• Defaults to VCLK as the source
• Frequency can be as fast as HCLK frequency
• Is disabled via the CDDISx registers bit 4
RTICLK VCLK RCLKSRC
• Defaults to VCLK as the source
• If a clock source other than VCLK is selected for RTICLK, then
the RTICLK frequency must be less than or equal to VCLK/3
– Application can ensure this by programming the RTI1DIV
field of the RCLKSRC register, if necessary
• Is disabled via the CDDISx registers bit 6
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