Datasheet

TMS570LS0432
TMS570LS0332
SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013 www.ti.com
4. Save the CPU state if required
5. Enable self-test.
6. Wait for CPU reset.
7. In the reset handler, read CPU self-test status to identify any failures.
8. Retrieve CPU state if required.
For more information refer to the device technical reference manual.
4.4.6.2 CPU Self-Test Clock Configuration
The maximum clock rate for the self-test is 45MHz. The STCCLK is divided down from the CPU clock,
when necessary. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.
For more information see the device Technical Reference Manual..
4.4.6.3 CPU Self-Test Coverage
Table 4-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test
cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.
Table 4-7. CPU Self-Test Coverage
INTERVALS TEST COVERAGE, % TEST CYCLES
0 0 0
1 60.06 1365
2 68.71 2730
3 73.35 4095
4 76.57 5460
5 78.7 6825
6 80.4 8190
7 81.76 9555
8 82.94 10920
9 83.84 12285
10 84.58 13650
11 85.31 15015
12 85.9 16380
13 86.59 17745
14 87.17 19110
15 87.67 20475
16 88.11 21840
17 88.53 23205
18 88.93 24570
19 89.26 25935
20 89.56 27300
21 89.86 28665
22 90.1 30030
23 90.36 31395
24 90.62 32760
25 90.86 34125
26 91.06 35490
30 System Information and Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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