Datasheet

North

Flip West

TMS570LS0432

TMS570LS0332

SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013

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4.4 ARM

Cortex-R4™ CPU Information

4.4.1 Summary of ARM Cortex-R4 CPU Features

The features of the ARM Cortex-R4™ CPU include:

• An integer unit with integral Embedded ICE-RT logic.

• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)

for Level two (L2) master and slave interfaces.

• Dynamic branch prediction with a global history buffer, and a 4-entry return stack

• Low interrupt latency.

• Non-maskable interrupt.

• A Harvard Level one (L1) memory system with:

– Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking

memories

– ARMv7-R architecture Memory Protection Unit (MPU) with 8 regions

• Dual core logic for fault detection in safety-critical applications.

• An L2 memory interface:

– Single 64-bit master AXI interface

– 64-bit slave AXI interface to TCM RAM blocks

• A debug interface to a CoreSight Debug Access Port (DAP).

• A Perfomance Monitoring Unit (PMU)

• A Vectored Interrupt Controller (VIC) port.

For more information on the ARM Cortex-R4 CPU please see www.arm.com.

4.4.2 ARM Cortex-R4 CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

• ECC On Tightly-Coupled Memory (TCM) Accesses

• Hardware Vectored Interrupt (VIC) Port

• Memory Protection Unit (MPU)

4.4.3 Dual Core Implementation

The device has two Cortex-R4 cores, where the output signals of both CPUs are compared in the CCM-

R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock

cycles as shown in Figure 4-3.

The CPUs have a diverse CPU placement given by following requirements:

• different orientation; e.g. CPU1 = "north" orientation, CPU2 = "flip west" orientation

• dedicated guard ring for each CPU

Figure 4-2. Dual - CPU Orientation

4.4.4 Duplicate clock tree after GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU

running at the same frequency and in phase to the clock of CPU1. See Figure 4-3.

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