Datasheet

TMS570LS0432

TMS570LS0332

www.ti.com

SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013

4.2 Power Sequencing and Power On Reset

4.2.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-

up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 4-4 for

more details), core voltage rising above the minimum core supply threshold and the release of power-on

reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The

oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The

different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

Table 4-3. Power-Up Phases

Oscillator start-up and validity check 1032 oscillator cycles

eFuse autoload 1160 oscillator cycles

Flash pump power-up 688 oscillator cycles

Flash bank power-up 617 oscillator cycles

Total 3497 oscillator cycles

The CPU reset is released at the end of the above sequence and fetches the first instruction from address

0x00000000.

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