Datasheet

t
f
t
r
V
CCIO
V
OH
V
OH
V
OL
V
OL
0
Output
TMS570LS0432
TMS570LS0332
www.ti.com SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013
Table 3-5. Switching Characteristics for Output Timings versus Load Capacitance ©
L
) (continued)
Parameter MIN MAX Unit
Rise time, t
r
4mA pins CL = 15 pF 5.6 ns
CL = 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Fall time, t
f
CL = 15 pF 5.6 ns
CL= 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Rise time, t
r
2mA-z pins CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Fall time, t
f
CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Rise time, t
r
Selectable 8mA / 2mA-z 8mA mode CL = 15 pF 2.5 ns
pins
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, t
f
CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Rise time, t
r
2mA-z mode CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Fall time, t
f
CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Figure 3-3. CMOS-Level Outputs
Table 3-6. Timing Requirements for Outputs
(1)
Parameter MIN MAX UNIT
t
d(parallel_out)
Delay between low to high, or high to low transition of general-purpose output signals 5 ns
that can be configured by an application in parallel, e.g. all signals in a GIOA port, or
all N2HET signals.
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check
Table 3-2for output buffer drive strength information on each signal.
Copyright © 2012–2013, Texas Instruments Incorporated Device Operating Conditions 23
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