Datasheet

V
CCIO
V
IH
V
IH
V
IL
0
Input
t
pw
V
IL
TMS570LS0432
TMS570LS0332
SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013 www.ti.com
Table 3-2. Output Buffer Drive Strengths (continued)
Low-level Output Current,
I
OL
for V
I
=V
OLmax
or Signals
High-level Output Current,
I
OH
for V
I
=V
OHmin
ECLK,
selectable 8mA / 2mA
SPI2CLK, SPI2SIMO, SPI2SOMI
The default output buffer drive strength is 8mA for these signals.
Table 3-3. Selectable 8ma/2ma Control
Signal Control Bit Address 8mA 2mA
ECLK SYSPC10[0] 0xFFFF FF78 0 1
SPI2CLK SPI2PC9[9]
(1)
0xFFF7 F668 0 1
SPI2SIMO SPI2PC9[10]
(1)
0xFFF7 F668 0 1
SPI2SOMI SPI2PC9[11]
(1)
0xFFF7 F668 0 1
(1) Do not do byte or half-word writes to SPI2PC9[31.16] as it may inadvertently change the drive strength of the SPI2 pins
3.8 Input Timings
Figure 3-2. TTL-Level Inputs
Table 3-4. Timing Requirements for Inputs
(1)
Parameter MIN MAX Unit
t
pw
Input minimum pulse width t
c(VCLK)
+ 10
(2)
ns
(1) t
c(VCLK)
= peripheral VBUS clock cycle time = 1 / f
(VCLK)
(2) The timing shown above is only valid for pin used in GIO mode.
3.9 Output Timings
Table 3-5. Switching Characteristics for Output Timings versus Load Capacitance ©
L
)
Parameter MIN MAX Unit
Rise time, t
r
8mA pins CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, t
f
CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
22 Device Operating Conditions Copyright © 2012–2013, Texas Instruments Incorporated
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