Datasheet

TMS570LS0432
TMS570LS0332
www.ti.com SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013
• Each byte in a PINMMR control register is used to select the functionality for a given pin. If the
application sets more than one bit within a byte for any pin, then the default function is selected for this
pin.
• Some bits within the PINMMR registers could be associated with internal pads that are not brought out
in the 100 pin package. As a result, bits marked reserved should not be written as a 1.
2.4 Special Multiplexed Options
Special controls are implemented to affect particular functions on this microcontroller. These controls are
described in this section.
2.4.1 Filtering for eQEP Inputs
2.4.1.1 eQEPA Input
• When PINMMR8[0] = 1, the eQEPA input is double-synchronized using VCLK.
• When PINMMR8[0] = 0 and PINMMR8[1] = 1, the eQEPA input is double-synchronized and then
qualified through a fixed 6-bit counter using VCLK.
• PINMMR8[0] = 0 and PINMMR8[1] = 0 is an illegal combination and behavior defaults to PINMMR8[0]
= 1.
2.4.1.2 eQEPB Input
• When PINMMR8[8] = 1, the eQEPB input is double-synchronized using VCLK.
• When PINMMR8[8] = 0 and PINMMR8[9] = 1, the eQEPB input is double-synchronized and then
qualified through a fixed 6-bit counter using VCLK.
• PINMMR8[8] = 0 and PINMMR8[9] = 0 is an illegal combination and behavior defaults to PINMMR8[8]
= 1.
2.4.1.3 eQEPI Input
• When PINMMR8[16] = 1, the eQEPI input is double-synchronized using VCLK.
• When PINMMR8[16] = 0 and PINMMR8[17] = 1, the eQEPI input is double-synchronized and then
qualified through a fixed 6-bit counter using VCLK.
• PINMMR8[16] = 0 and PINMMR8[17] = 0 is an illegal combination and behavior defaults to
PINMMR8[16] = 1.
2.4.1.4 eQEPS Input
• When PINMMR8[24] = 1, the eQEPS input is double-synchronized using VCLK.
• When PINMMR8[24] = 0 and PINMMR8[25] = 1, the eQEPS input is double-synchronized and then
qualified through a fixed 6-bit counter using VCLK.
• PINMMR8[24] = 0 and PINMMR8[25] = 0 is an illegal combination and behavior defaults to
PINMMR8[24] = 1.
2.4.2 N2HET PIN_nDISABLE Input Port
• When PINMMR9[0] = 1, GIOA[5] is connected directly to N2HET PIN_nDISABLE input of the N2HET
module.
• When PINMMR9[0] = 0 and PINMMR9[1] = 1, EQEPERR is inverted and double-synchronized using
VCLK before connecting directly to the N2HET PIN_nDISABLE input of the N2HET module.
• PINMMR9[0] = 0 and PINMMR9[1] = 0 is an illegal combination and behavior defaults to PINMMR9[0]
= 1.
Copyright © 2012–2013, Texas Instruments Incorporated Device Package and Terminal Functions 17
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