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TMS570LS0432

TMS570LS0332

www.ti.com

SPNS186A –OCTOBER 2012–REVISED SEPTEMBER 2013

TMS570LS0432/0332 16- and 32-Bit RISC Flash Microcontroller

Check for Samples: TMS570LS0432

1 TMS570LS0432/0332 16- and 32-Bit RISC Flash Microcontroller

1.1 Features

• High-Performance Automotive-Grade • Multiple Communication Interfaces

Microcontroller for Safety-Critical Applications

– Two CAN Controllers (DCANs)

– Dual CPUs Running in Lockstep

• DCAN1 - 32 Mailboxes with Parity

– ECC on Flash and RAM Interfaces Protection

– Built-In Self-Test for CPU and On-Chip RAMs • DCAN2 - 16 Mailboxes with Parity

Protection

– Error Signaling Module with Error Pin

• Compliant to CAN Protocol Version 2.0B

– Voltage and Clock Monitoring

– Multibuffered Serial Peripheral Interface

• ARM® Cortex™ – R4 32-Bit RISC CPU

(MibSPI) Module

– Efficient 1.66 DMIPS/MHz with 8-Stage

• 128 Words with Parity Protection

Pipeline

– Two Standard Serial Peripheral Interface

– 8-Region Memory Protection Unit

(SPI) Modules

– Open Architecture with Third-Party Support

– UART (SCI) Interface with Local Interconnect

• Operating Conditions

Network (LIN 2.1) Interface Support

– 80-MHz System Clock

• High-End Timer (N2HET) Module

– Core Supply Voltage (V

): 1.2-V Nominal

– Up to 19 Programmable Pins

– I/O Supply Voltage (V

CCIO

): 3.3-V Nominal

– 128-Word Instruction RAM with Parity

– ADC Supply Voltage (V

CCAD

): 3.3-V Nominal

Protection

• Integrated Memory

– Each Includes Hardware Angle Generator

– Up to 384KB of Program Flash with ECC

– Dedicated High-End Timer Transfer Unit

– 32KB of RAM with ECC

(HTU)

– 16KB of Flash for Emulated EEPROM with

• Enhanced Quadrature Encoder Pulse (eQEP)

ECC

Module

• Common Platform Architecture

– Motor Position Encoder Interface

– Consistent Memory Map Across Family

• 12-Bit Multibuffered Analog-to-Digital Converter

– Real-Time Interrupt (RTI) Timer (OS Timer)

(ADC) Module

– 96-Channel Vectored Interrupt Module (VIM)

– 16 Channels

– 2-Channel Cyclic Redundancy Checker

– 64 Result Buffers with Parity Protection

(CRC)

• Up to 45 General-Purpose I/O (GPIO) Capable

• Frequency-Modulated Phase-Locked Loop

Pins

(FMPLL) with Built-In Slip Detector

– 8 Dedicated GPIO Pins with up to 8 External

• IEEE 1149.1 JTAG, Boundary Scan and ARM

Interrupts

CoreSight™ Components

• Package

• Advanced JTAG Security Module (AJSM)

– 100-Pin Quad Flatpack (PZ) [Green]

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (106 pages)

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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 TMS570LS0432/0332 16- and 32-Bit RISC Flash Microcontroller Check for Samples: TMS570LS0432 1 TMS570LS0432/0332 16- and 32-Bit RISC Flash Microcontroller 1.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 1.2 • • • • • • • • 2 www.ti.
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TMS570LS0432 TMS570LS0332 www.ti.com 1.3 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Description The TMS570LS0432/0332 device is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and Memory Built-In Self Test (BIST) logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or external Error pin is triggered when a fault is detected. The nERROR can be monitored externally as an indicator of a fault condition in the microcontroller.
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TMS570LS0432 TMS570LS0332 www.ti.com 1.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 1 www.ti.com TMS570LS0432/0332 16- and 32-Bit RISC Flash Microcontroller .......................................... 1 ............................................. 1 1.2 Applications .......................................... 2 1.3 Description ........................................... 3 1.4 Functional Block Diagram ........................... 5 Revision History ..............................................
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the initial revision of the device-specific data manual to make it an A revision. Document Revision History Section Change Section 3.1 Increased absolute max voltage VCCIO and Input Voltage Section 3.2 Added maximum 3.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.
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TMS570LS0432 TMS570LS0332 www.ti.com 2.2 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Terminal Functions The following table identifies the external signal names, the associated pin numbers along with the mechanical package designator, the pin type (Input, Output, IO, Power or Ground), whether the pin has any internal pullup/pulldown, whether the pin can be configured as a GIO, and a functional pin description.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 2.2.1 www.ti.com High-End Timer (N2HET) Table 2-1.
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TMS570LS0432 TMS570LS0332 www.ti.com 2.2.3 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 General-Purpose Input/Output (GIO) Table 2-3. General-Purpose Input/Output (GIO) Terminal Signal Name 100 PZ GIOA[0]/SPI3nCS[3] 1 GIOA[1]/SPI3nCS[2] 2 GIOA[2]/SPI3nCS[1] 5 GIOA[3]/SPI2nCS[3] 8 GIOA[4]/SPI2nCS[2] 9 GIOA[5]/EXTCLKIN 10 GIOA[6]/SPI2nCS[1]/N2HET[31] 12 GIOA[7]/N2HET[29] 18 2.2.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 2.2.6 www.ti.com Standard Serial Peripheral Interface (SPI2) Table 2-6.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Table 2-8.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 2.2.11 Main Oscillator Table 2-11. Main Oscillator Terminal Signal Type Default Pull State Pull Type Description Signal Name 100 PZ OSCIN 14 Input - - From external crystal/resonator, or external clock input OSCOUT 16 Output - - To external crystal/resonator KELVIN_GND 15 Input - - Dedicated ground for oscillator 2.2.12 Test/Debug Interface Table 2-12.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 2.2.14 Core Supply Table 2-14. Core Supply Terminal Signal Name 100 PZ VCC 13 VCC 21 VCC 30 VCC 32 VCC 61 VCC 88 VCC 99 Signal Type Default Pull State Pull Type 1.2V Power - - Description Digital logic and RAM supply 2.2.15 I/O Supply Table 2-15. I/O Supply Terminal Signal Name 100 PZ VCCIO 6 VCCIO 28 VCCIO 60 VCCIO 85 Signal Type Default Pull State Pull Type 3.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 2.3 www.ti.com Output Multiplexing and Control Output multiplexing will be utilized in the device. The multiplexing is utilized to allow development of additional package/feature combinations as well as to maintain pinout compatibility with the marketing device family. In all cases indicated as multiplexed, the output buffers are multiplexed. Table 2-17.
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TMS570LS0432 TMS570LS0332 www.ti.com • • 2.4 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Each byte in a PINMMR control register is used to select the functionality for a given pin. If the application sets more than one bit within a byte for any pin, then the default function is selected for this pin. Some bits within the PINMMR registers could be associated with internal pads that are not brought out in the 100 pin package. As a result, bits marked reserved should not be written as a 1.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 3 Device Operating Conditions 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range, (1) VCC (2) Supply voltage range: VCCIO, VCCP Input voltage range: Input clamp current: -0.3 V to 1.43 V (2) -0.3 V to 4.6 V VCCAD -0.3 V to 3.6 V All input pins -0.3 V to 4.6 V ADC input pins -0.3 V to 4.
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TMS570LS0432 TMS570LS0332 www.ti.com 3.3 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Switching Characteristics over Recommended Operating Conditions for Clock Domains Table 3-1.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 3.5 www.ti.
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TMS570LS0432 TMS570LS0332 www.ti.com 3.6 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Input/Output Electrical Characteristics Over Recommended Operating Conditions (1) PARAMETER Vhys TEST CONDITIONS Input hysteresis MIN All inputs TYP (2) VIL Low-level input voltage All inputs VIH High-level input voltage All inputs (2) -0.3 0.8 V 2 VCCIO + 0.3 V VOH High-level output voltage IIC Input clamp current (I/O pins) II Input current (I/O pins) 0.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com Table 3-2. Output Buffer Drive Strengths (continued) Low-level Output Current, IOL for VI=VOLmax or High-level Output Current, IOH for VI=VOHmin Signals ECLK, selectable 8mA / 2mA SPI2CLK, SPI2SIMO, SPI2SOMI The default output buffer drive strength is 8mA for these signals. Table 3-3. Selectable 8ma/2ma Control Signal (1) 3.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Table 3-5. Switching Characteristics for Output Timings versus Load Capacitance ©L) (continued) Parameter Rise time, tr MIN 4mA pins Fall time, tf Rise time, tr 2mA-z pins Fall time, tf Rise time, tr Selectable 8mA / 2mA-z pins 8mA mode Fall time, tf Rise time, tr 2mA-z mode Fall time, tf MAX Unit CL = 15 pF 5.6 ns CL = 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 CL = 15 pF 5.6 CL= 50 pF 10.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 4 System Information and Electrical Specifications 4.1 Voltage Monitor Characteristics A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies. 4.1.1 Important Considerations • • 4.1.
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TMS570LS0432 TMS570LS0332 www.ti.com 4.2 4.2.1 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Power Sequencing and Power On Reset Power-Up Sequence There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The powerup sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 4-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.2.2 www.ti.com Power-Down Sequence The different supplies to the device can be powered down in any order. 4.2.3 Power-On Reset: nPORRST This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the recommended range. This signal has a glitch filter on it. It also has an internal pulldown. 4.2.3.1 nPORRST Electrical and Timing Requirements Table 4-4.
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TMS570LS0432 TMS570LS0332 www.ti.com 4.3 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Warm Reset (nRST) This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only).
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.4 4.4.1 www.ti.com ARM© Cortex-R4™ CPU Information Summary of ARM Cortex-R4 CPU Features The features of the ARM Cortex-R4™ CPU include: • An integer unit with integral Embedded ICE-RT logic. • High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
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TMS570LS0432 TMS570LS0332 www.ti.com 4.4.5 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 ARM Cortex-R4 CPU Compare Module (CCM) for Safety This device has two ARM Cortex-R4 CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in the figure below.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4. 5. 6. 7. 8. www.ti.com Save the CPU state if required Enable self-test. Wait for CPU reset. In the reset handler, read CPU self-test status to identify any failures. Retrieve CPU state if required. For more information refer to the device technical reference manual. 4.4.6.2 CPU Self-Test Clock Configuration The maximum clock rate for the self-test is 45MHz. The STCCLK is divided down from the CPU clock, when necessary.
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TMS570LS0432 TMS570LS0332 www.ti.com 4.5 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Clocks 4.5.1 Clock Sources The table below lists the available clock sources on the device. Each of the clock sources can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source. The table also shows the default state of each clock source. Table 4-8.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 4.5.1.1.1 Timing Requirements for Main Oscillator Table 4-9.
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TMS570LS0432 TMS570LS0332 www.ti.com 4.5.1.2 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Low Power Oscillator The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro. 4.5.1.2.1 Features The main features of the LPO are: • Supplies a clock at extremely low power for power-saving modes. This is connected as clock source # 4 of the Global Clock Module. • Supplies a high-frequency clock for non-timing-critical systems.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.5.1.3 www.ti.com Phase Locked Loop (PLL) Clock Modules The PLL is used to multiply the input frequency to some higher frequency. The main features of the PLL are: • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL. • Configurable frequency multipliers and dividers. • Built-in PLL Slip monitoring circuit. • Option to reset the device on a PLL slip detection. 4.5.1.3.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Table 4-12. Clock Domain Descriptions (continued) Clock Domain Name Default Clock Source Clock Source Selection Register Description VCLK OSCIN GHVSRC • • • • Divided down from HCLK Can be HCLK/1, HCLK/2, ...
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.5.2.2 www.ti.com Mapping of Clock Domains to Device Modules Each clock domain has a dedicated functionality as shown in the figure below. GCM 0 OSCIN FMzPLL /1..64 X1..256 /1..8 /1..32 1 * GCLK, GCLK2 (to CPU) HCLK (to SYSTEM) Low Power Oscillator 80kHz 4 10MHz 5 /1..16 3 /1..
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TMS570LS0432 TMS570LS0332 www.ti.com 4.5.3 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Clock Test Mode The TMS570 platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET[2] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured via the CLKTEST register in the system module. Table 4-13.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.6 www.ti.com Clock Monitoring The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low power oscillator (LPO). The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO). The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN).
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TMS570LS0432 TMS570LS0332 www.ti.com 4.6.3.2 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Mapping of DCC Clock Source Inputs Table 4-14. DCC Counter 0 Clock Sources TEST MODE 0 1 CLOCK SOURCE [3:0] CLOCK NAME others oscillator (OSCIN) 0x5 high frequency LPO 0xA test clock (TCK) X VCLK Table 4-15.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.7 www.ti.com Glitch Filters A glitch filter is present on the following signals. Table 4-16.
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TMS570LS0432 TMS570LS0332 www.ti.com 4.8 4.8.1 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Device Memory Map Memory Map Diagram The figure below shows the device memory map.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.
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TMS570LS0432 TMS570LS0332 www.ti.com 4.8.2 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Memory Map Table Please refer to Figure 1-1 for a block diagram showing the device interconnects. Table 4-17.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com Table 4-17. Device Memory Map (continued) ADDRESS RANGE FRAME ACTUA SIZE L SIZE RESPONSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME 0xFF47_FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Table 4-17.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.8.3 www.ti.com Master/Slave Access Privileges The table below lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device. Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed in the "MASTERS" column can access that slave module. Table 4-18.
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TMS570LS0432 TMS570LS0332 www.ti.com 4.9 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Flash Memory 4.9.1 Flash Memory Configuration Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic. Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.9.3 www.ti.com ECC Protection for Flash Accesses All accesses to the program flash memory are protected by Single Error Correction Double Error Detection (SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.10 Flash Program and Erase Timings for Program Flash Table 4-20. Timing Specifications for Program Flash Parameter tprog (144bit) Wide Word (144bit) programming time tprog (Total) 384KByte programming time (1) MIN Sector/Bank erase time (2) (1) (2) Unit 40 300 µs 4 s 2 s 1 -40°C to 125°C 0°C to 60°C, for first 25 cycles twec MAX -40°C to 125°C 0°C to 60°C, for first 25 cycles terase NOM 0.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 4.12 Tightly-Coupled RAM Interface Module Figure 4-11 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4™ CPU.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accesses to its RAM. NOTE The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 4.14 On-Chip SRAM Initialization and Testing 4.14.1 On-Chip SRAM Self-Test Using PBIST 4.14.1.1 Features • • • Extensive instruction set to support various memory test algorithms ROM-based algorithms allow application to run TI production-level memory tests Independent testing of all on-chip SRAM 4.14.1.2 PBIST RAM Groups Table 4-22.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.14.2 On-Chip SRAM Auto Initialization This microcontroller allows some of the on-chip memories to be initialized via the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 4.15 Vectored Interrupt Manager The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow of program execution.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Table 4-24.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 4.16 Real Time Interrupt Module The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code. The RTI module can incorporate several counters that define the timebases needed for scheduling an operating system.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 31 0 Update compare RTIUDCPy + 31 0 Compare RTICOMPy From counter block 0 = INTy From counter block 1 Compare control Figure 4-13. Compare Block Diagram 4.16.3 Clock Source Options The RTI module uses the RTICLK clock domain for generating the RTI time bases. The application can select the clock source for the RTICLK by configuring the RCLKSRC register in the System module at address 0xFFFFFF50.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 4.17 Error Signaling Module The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller. The error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used as an indicator to an external monitor circuit to put the system into a safe state. 4.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Table 4-26.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com Table 4-26.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Table 4-26.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 4.18 Reset / Abort / Error Sources Table 4-27. Reset/Abort/Error Sources ERROR SOURCE SYSTEM MODE ERROR RESPONSE ESM HOOKUP group.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Table 4-27. Reset/Abort/Error Sources (continued) ERROR SOURCE SYSTEM MODE ERROR RESPONSE ESM HOOKUP group.channel ESM 1.10 ESM 1.11 ESM 1.30 PLL PLL slip error User/Privilege CLOCK MONITOR Clock monitor interrupt User/Privilege DCC DCC error User/Privilege CCM-R4 Self test failure User/Privilege ESM 1.31 Compare failure User/Privilege ESM => NMI => nERROR 2.2 ESM 1.15 Reset n/a ESM 1.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 4.20 Debug Subsystem 4.20.1 Block Diagram The device contains an ICEPICK module to allow JTAG access to the scan chains. Boundary Scan I/F TRST TMS TCK RTCK TDI TDO Boundary Scan BSR/BSDL Debug ROM1 Debug APB Secondary Tap 0 DAP ICEPICK_C APB slave Cortex R4 Secondary Tap 2 AJSM Test Tap 0 eFuse Farm Figure 4-14. ZWT Debug Subsystem Block Diagram 4.20.2 Debug Components Memory Map Table 4-28.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.20.5 JTAG Scan Interface Timings Table 4-30. JTAG Scan Interface Timing (1) No.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 4.20.6 Advanced JTAG Security Module This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to the device’s memory content by allowing users to secure the device after programming. Flash Module Output OTP Contents (example) H L H ... ...
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 4.20.7 Boundary Scan Chain The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module. Device Pins (conceptual) RTCK TDI TDO IC E P ICK TRST TMS TCK Boundary Scan Interface Boundary Scan TDI TDO BSDL Figure 4-17.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 5 Peripheral Information and Electrical Specifications 5.1 Peripheral Legend Table 5-1. Peripheral Legend 5.
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TMS570LS0432 TMS570LS0332 www.ti.com • • 5.2.2 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Enhanced power-down mode – Optional feature to automatically power down ADC core when no conversion is in progress External event pin (ADEVT) programmable as general-purpose I/O Event Trigger Options The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3 groups can be configured to be hardware event-triggered.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 5.2.3 www.ti.com ADC Electrical and Timing Specifications Table 5-4. MibADC Recommended Operating Conditions Parameter MIN MAX Unit ADREFHI A-to-D high-voltage reference source ADREFLO VCCAD V ADREFLO A-to-D low-voltage reference source VSSAD ADREFHI V VAI Analog input voltage ADREFLO ADREFHI V IAIC Analog input clamp current (VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3) -2 2 mA Table 5-5.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Rext Pin VS1 Smux Rmux Smux Rmux 23*IAIL Cext On-State Leakage Rext Pin VS2 IAIL Cext IAIL IAIL Off-State Leakages Rext Pin Smux Rmux Ssamp Rsamp VS24 IAIL Csamp Cmux Cext IAIL IAIL Figure 5-1. MibADC Input Equivalent Circuit Table 5-6.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com Table 5-7. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions Parameter Description/Conditions CR Conversion range ADREFHI - ADREFLO over which specified accuracy is maintained ZSET Offset Error Difference between the first ideal transition (from code 000h to 001h) and the actual transition EDNL EINL ETOT Gain Error 10-bit mode Type Unit 3.
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TMS570LS0432 TMS570LS0332 www.ti.com 5.2.4 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Performance (Accuracy) Specifications 5.2.4.1 MibADC Nonlinearity Errors The differential nonlinearity error shown in Figure Figure 5-2 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB. 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 0 ... 011 Differential Linearity Error (–½ LSB) 1 LSB 0 ...
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com The integral nonlinearity error shown in Figure Figure 5-3 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. 0 ... 111 0 ... 110 Ideal Transition Digital Output Code 0 ... 101 Actual Transition 0 ... 100 At Transition 011/100 (–½ LSB) 0 ... 011 0 ... 010 End-Point Lin. Error 0 ... 001 At Transition 001/010 (–1/4 LSB) 0 ...
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TMS570LS0432 TMS570LS0332 www.ti.com 5.2.4.2 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 MibADC Total Error The absolute accuracy or total error of an MibADC as shown in Figure Figure 5-4 is the maximum value of the difference between an analog value and the ideal midstep value. 0 ... 111 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 Total Error At Step 0 ... 101 (–1 1/4 LSB) 0 ... 011 0 ... 010 Total Error At Step 0 ... 001 (1/2 LSB) 0 ... 001 0 ...
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 5.3 www.ti.com General-Purpose Input/Output The GPIO module on this device supports one port GIOA. The I/O pins are bidirectional and bitprogrammable. GIOA supports external interrupt capability. 5.3.
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TMS570LS0432 TMS570LS0332 www.ti.com 5.4 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Enhanced High-End Timer (N2HET) The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O..
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com Table 5-8.
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TMS570LS0432 TMS570LS0332 www.ti.com 5.4.6 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 High-End Timer Transfer Unit (N2HET) A High End Timer Transfer Unit (N2HET) can perform DMA type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the N2HET. 5.4.6.1 • • • • • • • • • 5.4.6.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 5.5 www.ti.com Controller Area Network (DCAN) The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (e.g.
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TMS570LS0432 TMS570LS0332 www.ti.com 5.6 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Local Interconnect Network Interface (LIN) The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility. The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn to zero format.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 5.7 www.ti.com Multi-Buffered / Standard Serial Peripheral Interface The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers, and analog-to-digital converters. 5.7.
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TMS570LS0432 TMS570LS0332 www.ti.com 5.7.3.1 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 MIBSPI1 Event Trigger Hookup Table 5-12.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 5.7.4 www.ti.com MibSPI/SPI Master Mode I/O Timing Specifications Table 5-13. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (2) (3) NO. 1 2 (5) 3 (5) 4 (5) 5 (5) 6 (5) 7 (5) 8 (6) 9 (6) (1) (2) (3) (4) (5) (6) 84 Parameter MIN MAX Unit 40 256tc(VCLK) ns Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 SPISIMO 5 Master Out Data Is Valid 6 7 Master In Data Must Be Valid SPISOMI Figure 5-6. SPI Master Mode External Timing (CLOCK PHASE = 0) Write to buffer SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure 5-7.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com Table 5-14. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (2) (3) NO. Parameter MIN MAX Unit 40 256tc(VCLK) ns Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 Master Out Data Is Valid SPISIMO 6 Data Valid 7 Master In Data Must Be Valid SPISOMI Figure 5-8. SPI Master Mode External Timing (CLOCK PHASE = 1) Write to buffer SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure 5-9.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 5.7.5 www.ti.com SPI Slave Mode I/O Timings Table 5-15. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (2) (3) (4) NO.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI Data Is Valid SPISOMI 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 5-10. SPI Slave Mode External Timing (CLOCK PHASE = 0) SPICLK (clock polarity=0) SPICLK (clock polarity=1) 8 SPIENAn 9 SPICSn Figure 5-11.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com Table 5-16. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (2) (3) (4) NO.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI SPISOMI Data Is Valid 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 5-12. SPI Slave Mode External Timing (CLOCK PHASE = 1) SPICLK (clock polarity=0) SPICLK (clock polarity=1) 8 SPIENAn 9 SPICSn 10 SPISOMI Slave Out Data Is Valid Figure 5-13.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 5.8 www.ti.com Enhanced Quadrature Encoder (eQEP) Figure 5-14 shows the eQEP module interconnections on the device. VBUSP Interface CDDISx.9 VCLK ACK CLKSTOP_REQ EQEP CLK GATE EQEPENCLK VCLK EQEPA EQEPB EQEPI EQEP Module EQEPIO EQEPIOE SYS_nRST EQEPS EQEPSOE nEQEPERR _SYNC NHET EQEPSO EQEPINTn VIM I/O MUX CTRL EQEPERR nDIS GIOA[5] VCLK2 NHETnDIS_SEL Figure 5-14. eQEP Module Interconnections 5.8.
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TMS570LS0432 TMS570LS0332 www.ti.com 5.8.4 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Enhanced Quadrature Encoder Pulse (eQEPx) Timing Table 5-18.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 6 Device and Documentation Support 6.1 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS.
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TMS570LS0432 TMS570LS0332 www.ti.com 6.2 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Device Identification The figure below illustrates the numbering and symbol nomenclature for the TMS570LS0432/0332 .
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com Figure 6-2.
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TMS570LS0432 TMS570LS0332 www.ti.com SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 Table 6-1. Device ID Bit Allocation Register Field Descriptions Bit Field 31 CP15 Value Description Indicates the presence of coprocessor 15 1 30-17 UNIQUE ID 16-13 TECH CP15 present 100100 Silicon version (revision) bits. This bitfield holds a unique number for a dedicated device configuration (die). Process technology on which the device is manufactured. 0101 12 I/O VOLTAGE I/O voltage of the device.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 6.4.1 www.ti.com DCAN Certification Figure 6-3.
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TMS570LS0432 TMS570LS0332 www.ti.com 6.4.2 6.4.2.1 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 LIN Certification LIN Master Mode Figure 6-4.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 6.4.2.2 www.ti.com LIN Slave Mode - Fixed Baud Rate Figure 6-5.
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TMS570LS0432 TMS570LS0332 www.ti.com 6.4.2.3 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 LIN Slave Mode - Adaptive Baud Rate Figure 6-6.
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TMS570LS0432 TMS570LS0332 SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013 www.ti.com 7 Mechanical Data 7.1 Thermal Data Table 7-1 shows the thermal resistance characteristics for the PQFP - PZ mechanical packages. Table 7-1. Thermal Resistance Characteristics (S-PQFP Package) [PZ] 7.2 PARAMETER °C/W RθJA 48 RθJC 5 Packaging Information The following packaging information reflects the most current released data available for the designated device(s).
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 20-Oct-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.