Datasheet
99
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com
SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
(1) Typical values are measured with V
REFHI
= 2.5 V and V
REFLO
= 0 V. Minimum and Maximum values are tested or characterized with
V
REFHI
= 2.5 V and V
REFLO
= 0 V.
(2) See Section 5.8.1.1.2.
(3) Difference from conversion result 32768 when ADCINp = ADCINn = V
REFCM
.
(4) No missing codes.
(5) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(6) IO activity is minimized on pins adjacent to ADC input and V
REFHI
pins as part of best practices to reduce capacitive coupling and
crosstalk.
(7) One ADC operating while all other ADCs are idle.
(8) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
(9) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
(10) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
(11) Value based on characterization.
Table 5-44. ADC Characteristics (16-Bit Differential Mode)
over recommended operating conditions (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC conversion cycles
(2)
29.6 31 ADCCLKs
Power-up time (after setting
ADCPWDNZ to first conversion)
500 µs
Gain error –64 ±9 64 LSBs
Offset error
(3)
–16 ±9 16 LSBs
Channel-to-channel gain error ±6 LSBs
Channel-to-channel offset error ±3 LSBs
ADC-to-ADC gain error Identical V
REFHI
and V
REFLO
for all ADCs ±6 LSBs
ADC-to-ADC offset error Identical V
REFHI
and V
REFLO
for all ADCs ±3 LSBs
DNL
(4)
> –1 ±0.5 1 LSBs
INL –3 ±1.5 3 LSBs
SNR
(5)(6)
V
REFHI
= 2.5 V, f
in
= 10 kHz 87.6 dB
THD
(5)(6)
V
REFHI
= 2.5 V, f
in
= 10 kHz –93.5 dB
SFDR
(5)(6)
V
REFHI
= 2.5 V, f
in
= 10 kHz 95.4 dB
SINAD
(5)(6)
V
REFHI
= 2.5 V, f
in
= 10 kHz 86.6 dB
ENOB
(5)(6)
V
REFHI
= 2.5 V, f
in
= 10 kHz,
single ADC
(7)
14.1
bits
V
REFHI
= 2.5 V, f
in
= 10 kHz,
synchronous ADCs
(8)
14.1
V
REFHI
= 2.5 V, f
in
= 10 kHz,
asynchronous ADCs
(9)
Not
supported
PSRR
V
DDA
= 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
77 dB
PSRR
V
DDA
= 3.3-V DC + 200 mV
Sine at 800 kHz
74 dB
CMRR DC to 1 MHz 60 dB
V
REFHI
input current 190 µA
ADC-to-ADC isolation
(6)(10)(11)
V
REFHI
= 2.5 V, synchronous ADCs
(8)
–2 2
LSBs
V
REFHI
= 2.5 V, asynchronous ADCs
(9)
Not
supported